// ****************************************************************************** 
// Copyright     :  Copyright (C) 2018, Hisilicon Technologies Co. Ltd.
// File name     :  hipciec_mac_reg_1_c_union_define.h
// Project line  :  Platform And Key Technologies Development
// Department    :  CAD Development Department
// Author        :  xxx
// Version       :  1.0
// Date          :  2017/10/24
// Description   :  The description of xxx project
// Others        :  Generated automatically by nManager V4.2 
// History       :  xxx 2018/03/16 18:02:55 Create file
// ******************************************************************************

#ifndef __HIPCIEC_MAC_REG_1_C_UNION_DEFINE_H__
#define __HIPCIEC_MAC_REG_1_C_UNION_DEFINE_H__

/* Define the union U_MAC_REQ_EIOS_TO_ELEIDLE_DELAY */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_0                     : 26  ; /* [31:6] */
        unsigned int    reg_eios_to_eleidle_delay : 6  ; /* [5:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_MAC_REQ_EIOS_TO_ELEIDLE_DELAY;

/* Define the union U_MAC_REG_ENTER_LOOPBACK */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_1                    : 6  ; /* [31:26] */
        unsigned int    reg_loopback_wait_time   : 10  ; /* [25:16] */
        unsigned int    rsv_2                    : 1  ; /* [15] */
        unsigned int    mac_loc_preset_sigle     : 4  ; /* [14:11] */
        unsigned int    enter_loop_con           : 1  ; /* [10] */
        unsigned int    loopback_master_check_st : 2  ; /* [9:8] */
        unsigned int    rsv_3                    : 3  ; /* [7:5] */
        unsigned int    dis_hotrst_sent_eieos_en : 1  ; /* [4] */
        unsigned int    reg_ds_l0_loopback_en    : 1  ; /* [3] */
        unsigned int    loopback_sent_eieos_en   : 1  ; /* [2] */
        unsigned int    reg_loopback_check_en    : 1  ; /* [1] */
        unsigned int    reg_enter_loopback       : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_MAC_REG_ENTER_LOOPBACK;

/* Define the union U_MAC_REG_RETRAIN_LINK */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_4                  : 26  ; /* [31:6] */
        unsigned int    max_dp_hw_req_redo_num : 4  ; /* [5:2] */
        unsigned int    reg_req_tx_eq          : 1  ; /* [1] */
        unsigned int    reg_retrain_pulse      : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_MAC_REG_RETRAIN_LINK;

/* Define the union U_MAC_REQ_TX_LINK_NUM */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_5           : 24  ; /* [31:8] */
        unsigned int    reg_tx_link_num : 8  ; /* [7:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_MAC_REQ_TX_LINK_NUM;

/* Define the union U_MAC_REQ_SCRAMBLE_DISABLE */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_6                      : 30  ; /* [31:2] */
        unsigned int    reg_scramble_disable_gen3  : 1  ; /* [1] */
        unsigned int    reg_scramble_disable_gen12 : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_MAC_REQ_SCRAMBLE_DISABLE;

/* Define the union U_MAC_REG_SKP_INTVAL_SRIS */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_7                    : 7  ; /* [31:25] */
        unsigned int    reg_skp_intvl_sris_gen3  : 9  ; /* [24:16] */
        unsigned int    rsv_8                    : 3  ; /* [15:13] */
        unsigned int    reg_skp_intvl_sris_gen12 : 13  ; /* [12:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_MAC_REG_SKP_INTVAL_SRIS;

/* Define the union U_MAC_REG_DC_BALANCE_DISABLE */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_9                  : 31  ; /* [31:1] */
        unsigned int    reg_dc_balance_disable : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_MAC_REG_DC_BALANCE_DISABLE;

/* Define the union U_MAC_REG_EQ_DISABLE */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_10                   : 30  ; /* [31:2] */
        unsigned int    reg_ds_eq_p23_disable    : 1  ; /* [1] */
        unsigned int    reg_equalization_disable : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_MAC_REG_EQ_DISABLE;

/* Define the union U_MAC_REG_SUPPORTED_TX_PRESET_BM */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_11                          : 16  ; /* [31:16] */
        unsigned int    reg_supported_tx_preset_bit_map : 16  ; /* [15:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_MAC_REG_SUPPORTED_TX_PRESET_BM;

/* Define the union U_MAC_REG_8G_PHY_EQ_FB_SEL */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_12                  : 17  ; /* [31:15] */
        unsigned int    cfg_8g_reset_eieos      : 1  ; /* [14] */
        unsigned int    cfg_8g_merit_step       : 6  ; /* [13:8] */
        unsigned int    rsv_13                  : 2  ; /* [7:6] */
        unsigned int    reg_8g_coeff_search_len : 4  ; /* [5:2] */
        unsigned int    reg_8g_phy_eq_fb_sel    : 2  ; /* [1:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_MAC_REG_8G_PHY_EQ_FB_SEL;

/* Define the union U_MAC_REG_GEN3_TX_COEFF_MAP_MODE */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_14                     : 30  ; /* [31:2] */
        unsigned int    reg_gen3_tx_coeff_map_mode : 2  ; /* [1:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_MAC_REG_GEN3_TX_COEFF_MAP_MODE;

/* Define the union U_MAC_REG_EQ_PHASE23_CONV_STEP_ADDR */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_15                   : 26  ; /* [31:6] */
        unsigned int    reg_eq_phase23_conv_step : 6  ; /* [5:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_MAC_REG_EQ_PHASE23_CONV_STEP_ADDR;

/* Define the union U_MAC_REG_EQ_PHASE23_TIMEOUT_VAL */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_16                    : 16  ; /* [31:16] */
        unsigned int    reg_eq_phase3_timeout_val : 8  ; /* [15:8] */
        unsigned int    reg_eq_phase2_timeout_val : 8  ; /* [7:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_MAC_REG_EQ_PHASE23_TIMEOUT_VAL;

/* Define the union U_MAC_REG_SKP_INTVAL_SRNS */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_17                   : 7  ; /* [31:25] */
        unsigned int    reg_skp_intvl_srns_gen3  : 9  ; /* [24:16] */
        unsigned int    rsv_18                   : 3  ; /* [15:13] */
        unsigned int    reg_skp_intvl_srns_gen12 : 13  ; /* [12:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_MAC_REG_SKP_INTVAL_SRNS;

/* Define the union U_MAC_REG_N_FTS */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_19         : 8  ; /* [31:24] */
        unsigned int    reg_n_fts_gen3 : 8  ; /* [23:16] */
        unsigned int    reg_n_fts_gen2 : 8  ; /* [15:8] */
        unsigned int    reg_n_fts_gen1 : 8  ; /* [7:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_MAC_REG_N_FTS;

/* Define the union U_MAC_REG_PHYSTATUS_DET_TIMEOUT_VAL */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_20                        : 22  ; /* [31:10] */
        unsigned int    reg_phystatus_det_timeout_val : 10  ; /* [9:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_MAC_REG_PHYSTATUS_DET_TIMEOUT_VAL;

/* Define the union U_MAC_REG_RDN_CROSS_TIMEOUT_VAL */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_21                       : 23  ; /* [31:9] */
        unsigned int    reg_random_cross_timeout_val : 9  ; /* [8:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_MAC_REG_RDN_CROSS_TIMEOUT_VAL;

/* Define the union U_MAC_REG_SEL_DEEMPH_US */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_22            : 30  ; /* [31:2] */
        unsigned int    reg_no_deemph     : 1  ; /* [1] */
        unsigned int    reg_sel_deemph_us : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_MAC_REG_SEL_DEEMPH_US;

/* Define the union U_MAC_REG_TX_COMP_RCV */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_23                : 31  ; /* [31:1] */
        unsigned int    reg_tx_compliance_rcv : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_MAC_REG_TX_COMP_RCV;

/* Define the union U_MAC_REG_TXSWING */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_24      : 31  ; /* [31:1] */
        unsigned int    reg_txswing : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_MAC_REG_TXSWING;

/* Define the union U_MAC_REG_LTSSM_TRACER_INPUT */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_25                    : 30  ; /* [31:2] */
        unsigned int    reg_ltssm_tracer_cap_mode : 1  ; /* [1] */
        unsigned int    reg_ltssm_tracer_recap    : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_MAC_REG_LTSSM_TRACER_INPUT;

/* Define the union U_MAC_REG_MAC_INT_STATUS */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_26                                  : 2  ; /* [31:30] */
        unsigned int    reg_enter_g4_recovery_speed_intr_status : 1  ; /* [29] */
        unsigned int    reg_enter_lpbk_lock_intr_status         : 1  ; /* [28] */
        unsigned int    reg_ltssm_intr_status                   : 1  ; /* [27] */
        unsigned int    reg_enter_g3_recovery_speed_intr_status : 1  ; /* [26] */
        unsigned int    reg_enter_g2_recovery_speed_intr_status : 1  ; /* [25] */
        unsigned int    reg_enter_g1_recovery_speed_intr_status : 1  ; /* [24] */
        unsigned int    ltssm_tracer_sram_ecc_2bit_err          : 1  ; /* [23] */
        unsigned int    ltssm_tracer_sram_ecc_1bit_err          : 1  ; /* [22] */
        unsigned int    pl_eco_rsv_intr_status                  : 4  ; /* [21:18] */
        unsigned int    reg_enter_eq_p3_intr_status             : 1  ; /* [17] */
        unsigned int    reg_enter_recovery_cfg_intr_status      : 1  ; /* [16] */
        unsigned int    reg_enter_recovery_lock_intr_status     : 1  ; /* [15] */
        unsigned int    reg_enter_l2_timeout_intr_status        : 1  ; /* [14] */
        unsigned int    reg_enter_l1_timeout_intr_status        : 1  ; /* [13] */
        unsigned int    reg_deskew_fifo_overflow_intr_status    : 1  ; /* [12] */
        unsigned int    reg_loopback_unlock_intr_status         : 1  ; /* [11] */
        unsigned int    reg_symbol_unlock_intr_status           : 1  ; /* [10] */
        unsigned int    reg_deskew_unlock_intr_status           : 1  ; /* [9] */
        unsigned int    reg_phystatus_timeout_intr_status       : 1  ; /* [8] */
        unsigned int    rxl0s_to_recovery_intr_status           : 1  ; /* [7] */
        unsigned int    reg_hot_reset_intr_status               : 1  ; /* [6] */
        unsigned int    reg_leave_disable_intr_status           : 1  ; /* [5] */
        unsigned int    reg_enter_disable_intr_status           : 1  ; /* [4] */
        unsigned int    reg_leave_l0_intr_status                : 1  ; /* [3] */
        unsigned int    reg_enter_l0_intr_status                : 1  ; /* [2] */
        unsigned int    reg_linkdown_intr_status                : 1  ; /* [1] */
        unsigned int    reg_linkup_intr_status                  : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_MAC_REG_MAC_INT_STATUS;

/* Define the union U_MAC_REG_MAC_INT_MASK */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    reg_intr_mask : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_MAC_REG_MAC_INT_MASK;

/* Define the union U_MAC_REG_TEST_COUNTER */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_27               : 16  ; /* [31:16] */
        unsigned int    phy_lane_err_counter : 16  ; /* [15:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_MAC_REG_TEST_COUNTER;

/* Define the union U_MAC_REG_LINK_INFO */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rx_deskew_st           : 2  ; /* [31:30] */
        unsigned int    mac_ltssm_st           : 6  ; /* [29:24] */
        unsigned int    rsv_28                 : 3  ; /* [23:21] */
        unsigned int    req_ending_txdata_en   : 1  ; /* [20] */
        unsigned int    lane_reverse           : 1  ; /* [19] */
        unsigned int    mac_descramble_disable : 1  ; /* [18] */
        unsigned int    is_upstream_port_ltssm : 1  ; /* [17] */
        unsigned int    mac_link_up            : 1  ; /* [16] */
        unsigned int    rx_eval_st             : 2  ; /* [15:14] */
        unsigned int    rxl0s_st               : 2  ; /* [13:12] */
        unsigned int    mac_cur_link_speed     : 4  ; /* [11:8] */
        unsigned int    rsv_29                 : 2  ; /* [7:6] */
        unsigned int    mac_cur_link_width     : 6  ; /* [5:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_MAC_REG_LINK_INFO;

/* Define the union U_MAC_REG_DEBUG_PIPE1 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_30             : 10  ; /* [31:22] */
        unsigned int    mac_ltssm_st       : 6  ; /* [21:16] */
        unsigned int    mac_txdetrx_loopbk : 16  ; /* [15:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_MAC_REG_DEBUG_PIPE1;

/* Define the union U_MAC_REG_DEBUG_PIPE2 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_31          : 2  ; /* [31:30] */
        unsigned int    mac_ltssm_st    : 6  ; /* [29:24] */
        unsigned int    mac_powerdown_1 : 24  ; /* [23:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_MAC_REG_DEBUG_PIPE2;

/* Define the union U_MAC_REG_DEBUG_PIPE3 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_32        : 10  ; /* [31:22] */
        unsigned int    mac_ltssm_st  : 6  ; /* [21:16] */
        unsigned int    phy_phystatus : 16  ; /* [15:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_MAC_REG_DEBUG_PIPE3;

/* Define the union U_MAC_REG_DEBUG_PIPE4 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_33                : 2  ; /* [31:30] */
        unsigned int    txdli_tx_buf_start    : 1  ; /* [29] */
        unsigned int    txdli_tx_buf_byte_cnt : 6  ; /* [28:23] */
        unsigned int    txdli_data_fifo_cnt   : 3  ; /* [22:20] */
        unsigned int    txdli_pkt_end         : 1  ; /* [19] */
        unsigned int    skp_acc_counter       : 5  ; /* [18:14] */
        unsigned int    mac_ltssm_st          : 6  ; /* [13:8] */
        unsigned int    rx_link_speed         : 5  ; /* [7:3] */
        unsigned int    rsv_34                : 1  ; /* [2] */
        unsigned int    mac_rate              : 2  ; /* [1:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_MAC_REG_DEBUG_PIPE4;

/* Define the union U_MAC_REG_DEBUG_RXDLI_1 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rxdli_st           : 1  ; /* [31] */
        unsigned int    mac_rx_data_enable : 1  ; /* [30] */
        unsigned int    mac_rx_null        : 2  ; /* [29:28] */
        unsigned int    mac_rx_err         : 4  ; /* [27:24] */
        unsigned int    mac_rx_end         : 8  ; /* [23:16] */
        unsigned int    mac_rx_str         : 16  ; /* [15:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_MAC_REG_DEBUG_RXDLI_1;

/* Define the union U_MAC_REG_DEBUG_LINK_NUM_1 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    cur_tx_link_num_1 : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_MAC_REG_DEBUG_LINK_NUM_1;

/* Define the union U_MAC_REG_DEBUG_LANE_NUM_1 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    cur_tx_lane_num_1 : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_MAC_REG_DEBUG_LANE_NUM_1;

/* Define the union U_MAC_REG_DEBUG_TXDLI */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_35             : 9  ; /* [31:23] */
        unsigned int    rxdli_bus_cnt      : 3  ; /* [22:20] */
        unsigned int    rxdli_have_tlp     : 1  ; /* [19] */
        unsigned int    rxdli_have_pkt     : 1  ; /* [18] */
        unsigned int    rxdli_data_offset  : 6  ; /* [17:12] */
        unsigned int    rxdli_str_offset   : 6  ; /* [11:6] */
        unsigned int    block_symbol_count : 4  ; /* [5:2] */
        unsigned int    tx_dli_fsm         : 2  ; /* [1:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_MAC_REG_DEBUG_TXDLI;

/* Define the union U_MAC_REG_LTSSM_TRACER_OUTPUT_1 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    suceessful_speed_negotiation                 : 1  ; /* [31] */
        unsigned int    changed_speed_recovery                       : 1  ; /* [30] */
        unsigned int    any_lane_rcv_speed_change                    : 1  ; /* [29] */
        unsigned int    rxl0s_to_recovery                            : 1  ; /* [28] */
        unsigned int    any_det_eieos_ts                             : 1  ; /* [27] */
        unsigned int    directed_speed_change                        : 1  ; /* [26] */
        unsigned int    all_phy_rxeleidle_or_rx_skp_interval_timeout : 1  ; /* [25] */
        unsigned int    dl_retrain                                   : 1  ; /* [24] */
        unsigned int    rcv_eios                                     : 1  ; /* [23] */
        unsigned int    any_change_pipe_req                          : 1  ; /* [22] */
        unsigned int    rxl0s_st                                     : 2  ; /* [21:20] */
        unsigned int    train_bit_map                                : 8  ; /* [19:12] */
        unsigned int    mac_rate                                     : 2  ; /* [11:10] */
        unsigned int    duration_counter                             : 4  ; /* [9:6] */
        unsigned int    ltssm_st                                     : 6  ; /* [5:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_MAC_REG_LTSSM_TRACER_OUTPUT_1;

/* Define the union U_MAC_REG_LTSSM_TRACER_LAST_ADDR */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_36                     : 25  ; /* [31:7] */
        unsigned int    ltssm_tracer_addr_rollback : 1  ; /* [6] */
        unsigned int    ltssm_tracer_last_waddr    : 6  ; /* [5:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_MAC_REG_LTSSM_TRACER_LAST_ADDR;

/* Define the union U_MAC_REG_SYMBOL_UNLOCL_COUNTER */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_37                : 16  ; /* [31:16] */
        unsigned int    symbol_unlock_counter : 16  ; /* [15:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_MAC_REG_SYMBOL_UNLOCL_COUNTER;

/* Define the union U_MAC_REG_MAC_INT_RO */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_38                                        : 2  ; /* [31:30] */
        unsigned int    reg_enter_g4_recovery_speed_intr_status_ro    : 1  ; /* [29] */
        unsigned int    reg_enter_lpbk_lock_intr_status_ro            : 1  ; /* [28] */
        unsigned int    reg_ltssm_intr_status_ro                      : 1  ; /* [27] */
        unsigned int    reg_enter_g3_recovery_speed_intr_status_ro    : 1  ; /* [26] */
        unsigned int    reg_enter_g2_recovery_speed_intr_status_ro    : 1  ; /* [25] */
        unsigned int    reg_enter_g1_recovery_speed_intr_status_ro    : 1  ; /* [24] */
        unsigned int    ltssm_tracer_sram_ecc_2bit_err_intr_status_ro : 1  ; /* [23] */
        unsigned int    ltssm_tracer_sram_ecc_1bit_err_intr_status_ro : 1  ; /* [22] */
        unsigned int    reg_eco_int_3                                 : 1  ; /* [21] */
        unsigned int    reg_eco_int_2                                 : 1  ; /* [20] */
        unsigned int    reg_eco_int_1                                 : 1  ; /* [19] */
        unsigned int    reg_eco_int_0                                 : 1  ; /* [18] */
        unsigned int    reg_enter_eq_p3_intr_status_ro                : 1  ; /* [17] */
        unsigned int    reg_enter_recovery_cfg_intr_status_ro         : 1  ; /* [16] */
        unsigned int    reg_enter_recovery_lock_intr_status_ro        : 1  ; /* [15] */
        unsigned int    reg_enter_l2_timeout_intr_status_ro           : 1  ; /* [14] */
        unsigned int    reg_enter_l1_timeout_intr_status_ro           : 1  ; /* [13] */
        unsigned int    reg_deskew_fifo_overflow_intr_status_ro       : 1  ; /* [12] */
        unsigned int    reg_loopback_unlock_intr_status_ro            : 1  ; /* [11] */
        unsigned int    reg_symbol_unlock_intr_status_ro              : 1  ; /* [10] */
        unsigned int    reg_deskew_unlock_intr_status_ro              : 1  ; /* [9] */
        unsigned int    reg_phystatus_timeout_intr_status_ro          : 1  ; /* [8] */
        unsigned int    rxl0s_to_recovery_intr_status_ro              : 1  ; /* [7] */
        unsigned int    reg_hot_reset_intr_status_ro                  : 1  ; /* [6] */
        unsigned int    reg_leave_disable_intr_status_ro              : 1  ; /* [5] */
        unsigned int    reg_enter_disable_intr_status_ro              : 1  ; /* [4] */
        unsigned int    reg_leave_l0_intr_status_ro                   : 1  ; /* [3] */
        unsigned int    reg_enter_l0_intr_status_ro                   : 1  ; /* [2] */
        unsigned int    reg_linkdown_intr_status_ro                   : 1  ; /* [1] */
        unsigned int    reg_linkup_intr_status_ro                     : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_MAC_REG_MAC_INT_RO;

/* Define the union U_MAC_REG_MAC_INT_SET */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_39                                   : 2  ; /* [31:30] */
        unsigned int    reg_enter_g4_recovery_speed_intr_set     : 1  ; /* [29] */
        unsigned int    reg_enter_lpbk_lock_intr_set             : 1  ; /* [28] */
        unsigned int    reg_ltssm_intr_set                       : 1  ; /* [27] */
        unsigned int    reg_enter_g3_recovery_speed_intr_set     : 1  ; /* [26] */
        unsigned int    reg_enter_g2_recovery_speed_intr_set     : 1  ; /* [25] */
        unsigned int    reg_enter_g1_recovery_speed_intr_set     : 1  ; /* [24] */
        unsigned int    ltssm_tracer_sram_ecc_2bit_err_intr_set  : 1  ; /* [23] */
        unsigned int    ltssm_tracer_sram_ecc_1bit_err_intr_set  : 1  ; /* [22] */
        unsigned int    eco_int_set_3                            : 1  ; /* [21] */
        unsigned int    eco_int_set_2                            : 1  ; /* [20] */
        unsigned int    eco_int_set_1                            : 1  ; /* [19] */
        unsigned int    eco_int_set_0                            : 1  ; /* [18] */
        unsigned int    reg_enter_eq_p3_intr_status_set          : 1  ; /* [17] */
        unsigned int    reg_enter_recovery_cfg_intr_status_set   : 1  ; /* [16] */
        unsigned int    reg_enter_recovery_lock_intr_status_set  : 1  ; /* [15] */
        unsigned int    reg_enter_l2_timeout_intr_status_set     : 1  ; /* [14] */
        unsigned int    reg_enter_l1_timeout_intr_status_set     : 1  ; /* [13] */
        unsigned int    reg_deskew_fifo_overflow_intr_status_set : 1  ; /* [12] */
        unsigned int    reg_loopback_unlock_intr_status_set      : 1  ; /* [11] */
        unsigned int    reg_symbol_unlock_intr_status_set        : 1  ; /* [10] */
        unsigned int    reg_deskew_unlock_intr_status_set        : 1  ; /* [9] */
        unsigned int    reg_phystatus_timeout_intr_status_set    : 1  ; /* [8] */
        unsigned int    rxl0s_to_recovery_intr_status_set        : 1  ; /* [7] */
        unsigned int    reg_hot_reset_intr_status_set            : 1  ; /* [6] */
        unsigned int    reg_leave_disable_intr_status_set        : 1  ; /* [5] */
        unsigned int    reg_enter_disable_intr_status_set        : 1  ; /* [4] */
        unsigned int    reg_leave_l0_intr_status_set             : 1  ; /* [3] */
        unsigned int    reg_enter_l0_intr_status_set             : 1  ; /* [2] */
        unsigned int    reg_linkdown_intr_status_set             : 1  ; /* [1] */
        unsigned int    reg_linkup_intr_status_set               : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_MAC_REG_MAC_INT_SET;

/* Define the union U_MAC_REG_ENTER_L1L2_TIMEOUT_VAL */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_40                     : 22  ; /* [31:10] */
        unsigned int    reg_enter_l1l2_timeout_val : 10  ; /* [9:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_MAC_REG_ENTER_L1L2_TIMEOUT_VAL;

/* Define the union U_MAC_REG_EQ_FIX_LP_TX_PRESET */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_41                             : 16  ; /* [31:16] */
        unsigned int    reg_comp_lpbk_remote_16g_tx_preset : 4  ; /* [15:12] */
        unsigned int    reg_comp_lpbk_remote_8g_tx_preset  : 4  ; /* [11:8] */
        unsigned int    reg_16g_eq_fix_lp_tx_preset        : 4  ; /* [7:4] */
        unsigned int    reg_8g_eq_fix_lp_tx_preset         : 4  ; /* [3:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_MAC_REG_EQ_FIX_LP_TX_PRESET;

/* Define the union U_MAC_REG_ADJ_HILINK_MODE_EN */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_42                                  : 1  ; /* [31] */
        unsigned int    reg_16g_ds_use_rx_preset_en             : 1  ; /* [30] */
        unsigned int    reg_16g_hilink_mode_en                  : 6  ; /* [29:24] */
        unsigned int    rsv_43                                  : 1  ; /* [23] */
        unsigned int    gen4_eq_phase23_ffe_ctle_adj_en         : 1  ; /* [22] */
        unsigned int    gen3_eq_phase23_ffe_ctle_adj_en         : 1  ; /* [21] */
        unsigned int    gen4_eq_phase01_ctle_apt_en             : 1  ; /* [20] */
        unsigned int    gen3_eq_phase01_ctle_apt_en             : 1  ; /* [19] */
        unsigned int    gen4_eq_phase23_ctle_apt_en             : 1  ; /* [18] */
        unsigned int    gen4_eq_rcv_lock_af_phase13_ctle_apt_en : 1  ; /* [17] */
        unsigned int    reg_switch_eq_mode_mask                 : 1  ; /* [16] */
        unsigned int    rcv_lock_hold_rate                      : 4  ; /* [15:12] */
        unsigned int    gen3_eq_phase23_ctle_apt_en             : 1  ; /* [11] */
        unsigned int    rcv_speed_pull_up_rx_preset_en          : 4  ; /* [10:7] */
        unsigned int    gen3_eq_rcv_lock_af_phase13_ctle_apt_en : 1  ; /* [6] */
        unsigned int    reg_8g_hilink_mode_en                   : 6  ; /* [5:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_MAC_REG_ADJ_HILINK_MODE_EN;

/* Define the union U_MAC_REG_LP_GEN3_TX_PRESET_P1_1 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    lp_gen3_tx_preset_p1_1 : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_MAC_REG_LP_GEN3_TX_PRESET_P1_1;

/* Define the union U_MAC_REG_EQ_OPT_TX_PRESET_1 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    opt_gen3_preset_1 : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_MAC_REG_EQ_OPT_TX_PRESET_1;

/* Define the union U_MAC_REG_LOOPBACK_PRESET_TIMEOUT_VAL_ADDR */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_44                          : 21  ; /* [31:11] */
        unsigned int    reg_loopback_preset_timeout_val : 11  ; /* [10:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_MAC_REG_LOOPBACK_PRESET_TIMEOUT_VAL_ADDR;

/* Define the union U_MAC_REG_COMP_OPTION */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_45             : 31  ; /* [31:1] */
        unsigned int    reg_comp_option_en : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_MAC_REG_COMP_OPTION;

/* Define the union U_MAC_REG_PHY_RXDATA_TS */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    phy_rxdata_ts : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_MAC_REG_PHY_RXDATA_TS;

/* Define the union U_MAC_REG_ECO_RSV0 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    mac_eco_rsv0 : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_MAC_REG_ECO_RSV0;

/* Define the union U_MAC_REG_ECO_RSV1 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    mac_eco_rsv1          : 31  ; /* [31:1] */
        unsigned int    reg_pm_irs_empty_mask : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_MAC_REG_ECO_RSV1;

/* Define the union U_MAC_REGEQ_TRACE */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_46                            : 4  ; /* [31:28] */
        unsigned int    coeff_search_tracer_lane_num      : 4  ; /* [27:24] */
        unsigned int    rsv_47                            : 1  ; /* [23] */
        unsigned int    coeff_search_tracer_addr_rollback : 1  ; /* [22] */
        unsigned int    coeff_search_tracer_last_waddr    : 6  ; /* [21:16] */
        unsigned int    rsv_48                            : 2  ; /* [15:14] */
        unsigned int    coeff_search_tracer_raddr         : 6  ; /* [13:8] */
        unsigned int    rsv_49                            : 5  ; /* [7:3] */
        unsigned int    coeff_search_tracer_mode          : 1  ; /* [2] */
        unsigned int    coeff_search_tracer_cap_mode      : 1  ; /* [1] */
        unsigned int    coeff_search_tracer_recap         : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_MAC_REGEQ_TRACE;

/* Define the union U_MAC_REG_EQ_TIMEOUT_SET */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_50                        : 13  ; /* [31:19] */
        unsigned int    cfg_coeff_req_timeout_val     : 11  ; /* [18:8] */
        unsigned int    cfg_coeff_search_22ms_timeout : 8  ; /* [7:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_MAC_REG_EQ_TIMEOUT_SET;

/* Define the union U_MAC_REG_EQ_INIT_COEFF_CFG */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_51                          : 4  ; /* [31:28] */
        unsigned int    preset_coeff_maping_table_index : 4  ; /* [27:24] */
        unsigned int    rsv_52                          : 6  ; /* [23:18] */
        unsigned int    cfg_init_coeff                  : 18  ; /* [17:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_MAC_REG_EQ_INIT_COEFF_CFG;

/* Define the union U_MAC_REG_WAIT_LINK_NUM_TIMER */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_53                 : 10  ; /* [31:22] */
        unsigned int    wait_ts1_num           : 6  ; /* [21:16] */
        unsigned int    rsv_54                 : 5  ; /* [15:11] */
        unsigned int    wait_link_num_timer_dp : 11  ; /* [10:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_MAC_REG_WAIT_LINK_NUM_TIMER;

/* Define the union U_MAC_REG_LANE_COEFF_1 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_55         : 10  ; /* [31:22] */
        unsigned int    reg_1_lane_c1  : 6  ; /* [21:16] */
        unsigned int    rsv_56         : 2  ; /* [15:14] */
        unsigned int    reg_1_lane_c0  : 6  ; /* [13:8] */
        unsigned int    rsv_57         : 2  ; /* [7:6] */
        unsigned int    reg_1_lane_cm1 : 6  ; /* [5:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_MAC_REG_LANE_COEFF_1;

/* Define the union U_MAC_REG_PRESET0 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_58          : 10  ; /* [31:22] */
        unsigned int    reg_preset0_c1  : 6  ; /* [21:16] */
        unsigned int    rsv_59          : 2  ; /* [15:14] */
        unsigned int    reg_preset0_c0  : 6  ; /* [13:8] */
        unsigned int    rsv_60          : 2  ; /* [7:6] */
        unsigned int    reg_preset0_cm1 : 6  ; /* [5:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_MAC_REG_PRESET0;

/* Define the union U_MAC_REG_PRESET1 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_61          : 10  ; /* [31:22] */
        unsigned int    reg_preset1_c1  : 6  ; /* [21:16] */
        unsigned int    rsv_62          : 2  ; /* [15:14] */
        unsigned int    reg_preset1_c0  : 6  ; /* [13:8] */
        unsigned int    rsv_63          : 2  ; /* [7:6] */
        unsigned int    reg_preset1_cm1 : 6  ; /* [5:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_MAC_REG_PRESET1;

/* Define the union U_MAC_REG_PRESET2 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_64          : 10  ; /* [31:22] */
        unsigned int    reg_preset2_c1  : 6  ; /* [21:16] */
        unsigned int    rsv_65          : 2  ; /* [15:14] */
        unsigned int    reg_preset2_c0  : 6  ; /* [13:8] */
        unsigned int    rsv_66          : 2  ; /* [7:6] */
        unsigned int    reg_preset2_cm1 : 6  ; /* [5:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_MAC_REG_PRESET2;

/* Define the union U_MAC_REG_PRESET3 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_67          : 10  ; /* [31:22] */
        unsigned int    reg_preset3_c1  : 6  ; /* [21:16] */
        unsigned int    rsv_68          : 2  ; /* [15:14] */
        unsigned int    reg_preset3_c0  : 6  ; /* [13:8] */
        unsigned int    rsv_69          : 2  ; /* [7:6] */
        unsigned int    reg_preset3_cm1 : 6  ; /* [5:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_MAC_REG_PRESET3;

/* Define the union U_MAC_REG_PRESET4 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_70          : 10  ; /* [31:22] */
        unsigned int    reg_preset4_c1  : 6  ; /* [21:16] */
        unsigned int    rsv_71          : 2  ; /* [15:14] */
        unsigned int    reg_preset4_c0  : 6  ; /* [13:8] */
        unsigned int    rsv_72          : 2  ; /* [7:6] */
        unsigned int    reg_preset4_cm1 : 6  ; /* [5:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_MAC_REG_PRESET4;

/* Define the union U_MAC_REG_PRESET5 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_73          : 10  ; /* [31:22] */
        unsigned int    reg_preset5_c1  : 6  ; /* [21:16] */
        unsigned int    rsv_74          : 2  ; /* [15:14] */
        unsigned int    reg_preset5_c0  : 6  ; /* [13:8] */
        unsigned int    rsv_75          : 2  ; /* [7:6] */
        unsigned int    reg_preset5_cm1 : 6  ; /* [5:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_MAC_REG_PRESET5;

/* Define the union U_MAC_REG_PRESET6 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_76          : 10  ; /* [31:22] */
        unsigned int    reg_preset6_c1  : 6  ; /* [21:16] */
        unsigned int    rsv_77          : 2  ; /* [15:14] */
        unsigned int    reg_preset6_c0  : 6  ; /* [13:8] */
        unsigned int    rsv_78          : 2  ; /* [7:6] */
        unsigned int    reg_preset6_cm1 : 6  ; /* [5:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_MAC_REG_PRESET6;

/* Define the union U_MAC_REG_PRESET7 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_79          : 10  ; /* [31:22] */
        unsigned int    reg_preset7_c1  : 6  ; /* [21:16] */
        unsigned int    rsv_80          : 2  ; /* [15:14] */
        unsigned int    reg_preset7_c0  : 6  ; /* [13:8] */
        unsigned int    rsv_81          : 2  ; /* [7:6] */
        unsigned int    reg_preset7_cm1 : 6  ; /* [5:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_MAC_REG_PRESET7;

/* Define the union U_MAC_REG_PRESET8 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_82          : 10  ; /* [31:22] */
        unsigned int    reg_preset8_c1  : 6  ; /* [21:16] */
        unsigned int    rsv_83          : 2  ; /* [15:14] */
        unsigned int    reg_preset8_c0  : 6  ; /* [13:8] */
        unsigned int    rsv_84          : 2  ; /* [7:6] */
        unsigned int    reg_preset8_cm1 : 6  ; /* [5:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_MAC_REG_PRESET8;

/* Define the union U_MAC_REG_PRESET9 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_85          : 10  ; /* [31:22] */
        unsigned int    reg_preset9_c1  : 6  ; /* [21:16] */
        unsigned int    rsv_86          : 2  ; /* [15:14] */
        unsigned int    reg_preset9_c0  : 6  ; /* [13:8] */
        unsigned int    rsv_87          : 2  ; /* [7:6] */
        unsigned int    reg_preset9_cm1 : 6  ; /* [5:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_MAC_REG_PRESET9;

/* Define the union U_MAC_REG_PRESET10 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_88           : 10  ; /* [31:22] */
        unsigned int    reg_preset10_c1  : 6  ; /* [21:16] */
        unsigned int    rsv_89           : 2  ; /* [15:14] */
        unsigned int    reg_preset10_c0  : 6  ; /* [13:8] */
        unsigned int    rsv_90           : 2  ; /* [7:6] */
        unsigned int    reg_preset10_cm1 : 6  ; /* [5:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_MAC_REG_PRESET10;

/* Define the union U_MAC_REG_PRESET11 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_91           : 10  ; /* [31:22] */
        unsigned int    reg_preset11_c1  : 6  ; /* [21:16] */
        unsigned int    rsv_92           : 2  ; /* [15:14] */
        unsigned int    reg_preset11_c0  : 6  ; /* [13:8] */
        unsigned int    rsv_93           : 2  ; /* [7:6] */
        unsigned int    reg_preset11_cm1 : 6  ; /* [5:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_MAC_REG_PRESET11;

/* Define the union U_MAC_REG_PRESET12 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_94           : 10  ; /* [31:22] */
        unsigned int    reg_preset12_c1  : 6  ; /* [21:16] */
        unsigned int    rsv_95           : 2  ; /* [15:14] */
        unsigned int    reg_preset12_c0  : 6  ; /* [13:8] */
        unsigned int    rsv_96           : 2  ; /* [7:6] */
        unsigned int    reg_preset12_cm1 : 6  ; /* [5:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_MAC_REG_PRESET12;

/* Define the union U_MAC_REG_PRESET13 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_97           : 10  ; /* [31:22] */
        unsigned int    reg_preset13_c1  : 6  ; /* [21:16] */
        unsigned int    rsv_98           : 2  ; /* [15:14] */
        unsigned int    reg_preset13_c0  : 6  ; /* [13:8] */
        unsigned int    rsv_99           : 2  ; /* [7:6] */
        unsigned int    reg_preset13_cm1 : 6  ; /* [5:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_MAC_REG_PRESET13;

/* Define the union U_MAC_REG_PRESET14 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_100          : 10  ; /* [31:22] */
        unsigned int    reg_preset14_c1  : 6  ; /* [21:16] */
        unsigned int    rsv_101          : 2  ; /* [15:14] */
        unsigned int    reg_preset14_c0  : 6  ; /* [13:8] */
        unsigned int    rsv_102          : 2  ; /* [7:6] */
        unsigned int    reg_preset14_cm1 : 6  ; /* [5:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_MAC_REG_PRESET14;

/* Define the union U_MAC_REG_PRESET15 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_103          : 10  ; /* [31:22] */
        unsigned int    reg_preset15_c1  : 6  ; /* [21:16] */
        unsigned int    rsv_104          : 2  ; /* [15:14] */
        unsigned int    reg_preset15_c0  : 6  ; /* [13:8] */
        unsigned int    rsv_105          : 2  ; /* [7:6] */
        unsigned int    reg_preset15_cm1 : 6  ; /* [5:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_MAC_REG_PRESET15;

/* Define the union U_MAC_REG_DEBUG_PIPE5 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_106       : 10  ; /* [31:22] */
        unsigned int    mac_ltssm_st  : 6  ; /* [21:16] */
        unsigned int    mac_txeleidle : 16  ; /* [15:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_MAC_REG_DEBUG_PIPE5;

/* Define the union U_MAC_REG_DEBUG_PIPE6 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_107        : 10  ; /* [31:22] */
        unsigned int    mac_ltssm_st   : 6  ; /* [21:16] */
        unsigned int    mac_rxpolarity : 16  ; /* [15:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_MAC_REG_DEBUG_PIPE6;

/* Define the union U_MAC_REG_DEBUG_PIPE7 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_108         : 2  ; /* [31:30] */
        unsigned int    mac_ltssm_st    : 6  ; /* [29:24] */
        unsigned int    mac_powerdown_1 : 24  ; /* [23:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_MAC_REG_DEBUG_PIPE7;

/* Define the union U_MAC_REG_DEBUG_PIPE8 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_109      : 10  ; /* [31:22] */
        unsigned int    mac_ltssm_st : 6  ; /* [21:16] */
        unsigned int    phy_txdetrx  : 16  ; /* [15:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_MAC_REG_DEBUG_PIPE8;

/* Define the union U_MAC_REG_DEBUG_PIPE9 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_110       : 10  ; /* [31:22] */
        unsigned int    mac_ltssm_st  : 6  ; /* [21:16] */
        unsigned int    phy_rxeleidle : 16  ; /* [15:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_MAC_REG_DEBUG_PIPE9;

/* Define the union U_MAC_REG_DEBUG_PIPE10 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_111          : 10  ; /* [31:22] */
        unsigned int    mac_ltssm_st     : 6  ; /* [21:16] */
        unsigned int    phy_rxdata_valid : 16  ; /* [15:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_MAC_REG_DEBUG_PIPE10;

/* Define the union U_MAC_REG_DEBUG_PIPE11 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_112      : 10  ; /* [31:22] */
        unsigned int    mac_ltssm_st : 6  ; /* [21:16] */
        unsigned int    phy_rxvalid  : 16  ; /* [15:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_MAC_REG_DEBUG_PIPE11;

/* Define the union U_MAC_REG_DEBUG_RXDLI_2 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_113    : 8  ; /* [31:24] */
        unsigned int    mac_rx_seq : 24  ; /* [23:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_MAC_REG_DEBUG_RXDLI_2;

/* Define the union U_MAC_REG_DEBUG_LINK_NUM_2 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    cur_tx_link_num_2 : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_MAC_REG_DEBUG_LINK_NUM_2;

/* Define the union U_MAC_REG_DEBUG_LINK_NUM_3 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    cur_tx_link_num_3 : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_MAC_REG_DEBUG_LINK_NUM_3;

/* Define the union U_MAC_REG_DEBUG_LINK_NUM_4 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    cur_tx_link_num_4 : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_MAC_REG_DEBUG_LINK_NUM_4;

/* Define the union U_MAC_REG_DEBUG_LANE_NUM_2 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    cur_tx_lane_num_2 : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_MAC_REG_DEBUG_LANE_NUM_2;

/* Define the union U_MAC_REG_DEBUG_LANE_NUM_3 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    cur_tx_lane_num_3 : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_MAC_REG_DEBUG_LANE_NUM_3;

/* Define the union U_MAC_REG_DEBUG_LANE_NUM_4 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    cur_tx_lane_num_4 : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_MAC_REG_DEBUG_LANE_NUM_4;

/* Define the union U_MAC_REG_LP_GEN3_TX_PRESET_P1_2 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    lp_gen3_tx_preset_p1_2 : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_MAC_REG_LP_GEN3_TX_PRESET_P1_2;

/* Define the union U_MAC_REG_GEN3_EQ_OPT_TX_PRESET_2 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    opt_gen3_preset_2 : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_MAC_REG_GEN3_EQ_OPT_TX_PRESET_2;

/* Define the union U_MAC_REG_LANE_COEFF_2 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_114        : 10  ; /* [31:22] */
        unsigned int    reg_2_lane_c1  : 6  ; /* [21:16] */
        unsigned int    rsv_115        : 2  ; /* [15:14] */
        unsigned int    reg_2_lane_c0  : 6  ; /* [13:8] */
        unsigned int    rsv_116        : 2  ; /* [7:6] */
        unsigned int    reg_2_lane_cm1 : 6  ; /* [5:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_MAC_REG_LANE_COEFF_2;

/* Define the union U_MAC_REG_LTSSM_TRACER_OUTPUT_2 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    txdetrx       : 16  ; /* [31:16] */
        unsigned int    train_bit_map : 16  ; /* [15:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_MAC_REG_LTSSM_TRACER_OUTPUT_2;

/* Define the union U_MAC_REG_LTSSM_TRACER_OUTPUT_OK */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_117              : 31  ; /* [31:1] */
        unsigned int    ltssm_tracer_data_ok : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_MAC_REG_LTSSM_TRACER_OUTPUT_OK;

/* Define the union U_MAC_REG_LTSSM_TRACER_SRAM_ECC_INSERT */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_118                      : 30  ; /* [31:2] */
        unsigned int    ltssm_tracer_sram_ecc_insert : 2  ; /* [1:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_MAC_REG_LTSSM_TRACER_SRAM_ECC_INSERT;

/* Define the union U_MAC_REG_LTSSM_TRACER_ECC_ERR_ADDR */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_119           : 18  ; /* [31:14] */
        unsigned int    ecc_2bit_err_addr : 6  ; /* [13:8] */
        unsigned int    rsv_120           : 2  ; /* [7:6] */
        unsigned int    ecc_1bit_err_addr : 6  ; /* [5:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_MAC_REG_LTSSM_TRACER_ECC_ERR_ADDR;

/* Define the union U_MAC_REG_COEFF_SEARCH_TRACER_OUTPUT */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    req_pre_cur_coeff     : 6  ; /* [31:26] */
        unsigned int    req_cur_coeff         : 6  ; /* [25:20] */
        unsigned int    fig_merit_feedback    : 8  ; /* [19:12] */
        unsigned int    rsv_121               : 3  ; /* [11:9] */
        unsigned int    fsm_curr_search_state : 3  ; /* [8:6] */
        unsigned int    total_search_num      : 6  ; /* [5:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_MAC_REG_COEFF_SEARCH_TRACER_OUTPUT;

/* Define the union U_MAC_REG_REMOTE_FS_LF */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_122   : 20  ; /* [31:12] */
        unsigned int    remote_fs : 6  ; /* [11:6] */
        unsigned int    remote_lf : 6  ; /* [5:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_MAC_REG_REMOTE_FS_LF;

/* Define the union U_MAC_LOOP_LINK_DATA_ERR_COUNT */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_123                     : 16  ; /* [31:16] */
        unsigned int    loop_back_link_data_err_cnt : 16  ; /* [15:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_MAC_LOOP_LINK_DATA_ERR_COUNT;

/* Define the union U_MAC_PCS_RX_ERR_CNT */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_124        : 16  ; /* [31:16] */
        unsigned int    pcs_rx_err_cnt : 16  ; /* [15:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_MAC_PCS_RX_ERR_CNT;

/* Define the union U_MAC_UP_MAX_AUTO_REDO_NUM */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_125                 : 18  ; /* [31:14] */
        unsigned int    req_rx_req_eq_ts_count  : 6  ; /* [13:8] */
        unsigned int    rsv_126                 : 4  ; /* [7:4] */
        unsigned int    req_dp_redo_eq_gnt_mask : 1  ; /* [3] */
        unsigned int    permit_up_redo_eq       : 1  ; /* [2] */
        unsigned int    rsv_127                 : 2  ; /* [1:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_MAC_UP_MAX_AUTO_REDO_NUM;

/* Define the union U_MAC_WAIT_LANE_NUM_TIMER */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_128                     : 2  ; /* [31:30] */
        unsigned int    cfg_lnacc_wait_lane_ts1_num : 6  ; /* [29:24] */
        unsigned int    rsv_129                     : 2  ; /* [23:22] */
        unsigned int    cfg_wait_lane_ts1_num       : 6  ; /* [21:16] */
        unsigned int    rsv_130                     : 5  ; /* [15:11] */
        unsigned int    cfg_wait_lane_num_timer_dp  : 11  ; /* [10:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_MAC_WAIT_LANE_NUM_TIMER;

/* Define the union U_MAC_LANE_NUM_WAIT_TIMER */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_131                 : 5  ; /* [31:27] */
        unsigned int    wait_link_num_timer_up  : 11  ; /* [26:16] */
        unsigned int    rsv_132                 : 5  ; /* [15:11] */
        unsigned int    reg_lane_num_wait_timer : 11  ; /* [10:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_MAC_LANE_NUM_WAIT_TIMER;

/* Define the union U_MAC_LANE_NUM_ACC_TIMER */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_133                    : 5  ; /* [31:27] */
        unsigned int    cfg_wait_lane_num_timer_up : 11  ; /* [26:16] */
        unsigned int    rsv_134                    : 5  ; /* [15:11] */
        unsigned int    reg_lane_num_acc_timer     : 11  ; /* [10:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_MAC_LANE_NUM_ACC_TIMER;

/* Define the union U_MAC_LNW_TO_LNA_1MS_TIMER */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_135                  : 21  ; /* [31:11] */
        unsigned int    cfg_lnw_to_lna_1ms_timer : 11  ; /* [10:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_MAC_LNW_TO_LNA_1MS_TIMER;

/* Define the union U_MAC_EQ_LTSMM_HOLD_TIMER */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_136                 : 10  ; /* [31:22] */
        unsigned int    cfg_phase0_hold_timer   : 6  ; /* [21:16] */
        unsigned int    rsv_137                 : 1  ; /* [15] */
        unsigned int    cfg_rcv_lock_hold_timer : 7  ; /* [14:8] */
        unsigned int    rsv_138                 : 1  ; /* [7] */
        unsigned int    cfg_phase23_hold_timer  : 7  ; /* [6:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_MAC_EQ_LTSMM_HOLD_TIMER;

/* Define the union U_MAC_LTSSM_CRTL_INFER_ELECIDLE */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_139                                : 28  ; /* [31:4] */
        unsigned int    reg_mask_datapath_rxelecidle           : 1  ; /* [3] */
        unsigned int    reg_use_any_lane_infer_eleidle         : 1  ; /* [2] */
        unsigned int    set_rx_elecidle_infer                  : 1  ; /* [1] */
        unsigned int    rx_elecidle_infer_interval_timout_mask : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_MAC_LTSSM_CRTL_INFER_ELECIDLE;

/* Define the union U_MAC_LTSSM_TRACER_CFG0 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    sel_trace_rx_data_mode    : 8  ; /* [31:24] */
        unsigned int    rsv_140                   : 4  ; /* [23:20] */
        unsigned int    ltssm_trace_lane_num      : 4  ; /* [19:16] */
        unsigned int    rsv_141                   : 6  ; /* [15:10] */
        unsigned int    ltssm_trace_timer_clk_sel : 1  ; /* [9] */
        unsigned int    rsv_142                   : 3  ; /* [8:6] */
        unsigned int    ltssm_trace_signal_mask   : 6  ; /* [5:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_MAC_LTSSM_TRACER_CFG0;

/* Define the union U_MAC_LTSSM_TRACER_CFG1 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_143                   : 7  ; /* [31:25] */
        unsigned int    clr_ltssm_trace_timer     : 1  ; /* [24] */
        unsigned int    rsv_144                   : 2  ; /* [23:22] */
        unsigned int    ltssm_trace_state         : 6  ; /* [21:16] */
        unsigned int    rsv_145                   : 5  ; /* [15:11] */
        unsigned int    ltssm_trace_trigger_timer : 11  ; /* [10:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_MAC_LTSSM_TRACER_CFG1;

/* Define the union U_MAC_CMP_LOOP_SENT_EQTS1 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_146                : 31  ; /* [31:1] */
        unsigned int    reg_mac_tx_sent_eq_ts1 : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_MAC_CMP_LOOP_SENT_EQTS1;

/* Define the union U_MAC_ENTER_LPBK_DISABLE */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_147                    : 17  ; /* [31:15] */
        unsigned int    disable_scramber_disable   : 1  ; /* [14] */
        unsigned int    reg_new_gen4_eieos_en      : 1  ; /* [13] */
        unsigned int    reg_disable_ctrl_skp       : 1  ; /* [12] */
        unsigned int    gen3_low_latency_mode      : 1  ; /* [11] */
        unsigned int    disable_enter_compliance   : 1  ; /* [10] */
        unsigned int    auto_speed_change_en       : 1  ; /* [9] */
        unsigned int    first_auto_speed_change_en : 1  ; /* [8] */
        unsigned int    auto_speed_disable_mask    : 1  ; /* [7] */
        unsigned int    disable_enter_hotreset     : 1  ; /* [6] */
        unsigned int    disable_enter_disable      : 3  ; /* [5:3] */
        unsigned int    disable_enter_loopback     : 3  ; /* [2:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_MAC_ENTER_LPBK_DISABLE;

/* Define the union U_MAC_PRESET_TABLE0 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    mac_preset_table0 : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_MAC_PRESET_TABLE0;

/* Define the union U_MAC_PRESET_TABLE1 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_148           : 12  ; /* [31:20] */
        unsigned int    reg_preset_num    : 4  ; /* [19:16] */
        unsigned int    rsv_149           : 4  ; /* [15:12] */
        unsigned int    mac_preset_table1 : 12  ; /* [11:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_MAC_PRESET_TABLE1;

/* Define the union U_MAC_REG_LTSSM_TRACERADDR */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_150                : 26  ; /* [31:6] */
        unsigned int    reg_ltssm_tracer_raddr : 6  ; /* [5:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_MAC_REG_LTSSM_TRACERADDR;

/* Define the union U_MAC_CFG_COMPLETE_TIMER */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_151                   : 15  ; /* [31:17] */
        unsigned int    cfg_clp_to_idle_tm_enable : 1  ; /* [16] */
        unsigned int    rsv_152                   : 5  ; /* [15:11] */
        unsigned int    reg_clp_to_idle_timer     : 11  ; /* [10:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_MAC_CFG_COMPLETE_TIMER;

/* Define the union U_MAC_CFG_COMP_ERRATA_DISABLE */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_153                 : 31  ; /* [31:1] */
        unsigned int    reg_comp_errata_disable : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_MAC_CFG_COMP_ERRATA_DISABLE;

/* Define the union U_MAC_RX_ERR_CHECK_EN */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_154              : 16  ; /* [31:16] */
        unsigned int    lane_rx_err_check_en : 16  ; /* [15:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_MAC_RX_ERR_CHECK_EN;

/* Define the union U_MAC_TRACE_2BIT_ECC_CNT */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_155         : 27  ; /* [31:5] */
        unsigned int    ecc_2bit_er_cnt : 5  ; /* [4:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_MAC_TRACE_2BIT_ECC_CNT;

/* Define the union U_MAC_TRACE_1BIT_ECC_CNT */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_156         : 27  ; /* [31:5] */
        unsigned int    ecc_1bit_er_cnt : 5  ; /* [4:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_MAC_TRACE_1BIT_ECC_CNT;

/* Define the union U_MAC_CFG_RCV_HOLD_EN */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_157              : 29  ; /* [31:3] */
        unsigned int    reg_rcv_idle_hold_en : 1  ; /* [2] */
        unsigned int    reg_rcv_cfg_hold_en  : 1  ; /* [1] */
        unsigned int    reg_rcv_lock_hold_en : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_MAC_CFG_RCV_HOLD_EN;

/* Define the union U_MAC_CFG_RCV_LOCK_HOLD_TIME */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_158                : 21  ; /* [31:11] */
        unsigned int    reg_rcv_lock_hold_time : 11  ; /* [10:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_MAC_CFG_RCV_LOCK_HOLD_TIME;

/* Define the union U_MAC_CFG_RCV_CFG_HOLD_TIME */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_159                : 4  ; /* [31:28] */
        unsigned int    reg_extended_ts_number : 12  ; /* [27:16] */
        unsigned int    rsv_160                : 5  ; /* [15:11] */
        unsigned int    reg_rcv_cfg_hold_time  : 11  ; /* [10:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_MAC_CFG_RCV_CFG_HOLD_TIME;

/* Define the union U_MAC_CFG_RCV_IDLE_HOLD_TIME */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_161                : 6  ; /* [31:26] */
        unsigned int    reg_detect_wait_time   : 10  ; /* [25:16] */
        unsigned int    rsv_162                : 5  ; /* [15:11] */
        unsigned int    reg_rcv_idle_hold_time : 11  ; /* [10:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_MAC_CFG_RCV_IDLE_HOLD_TIME;

/* Define the union U_MAC_LTSSM_INT_STATUS */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_163                   : 26  ; /* [31:6] */
        unsigned int    reg_ltssm_int_match_state : 6  ; /* [5:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_MAC_LTSSM_INT_STATUS;

/* Define the union U_MAC_DESKEW_SYMBOL_UNLOCK_RCV_MASK */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_164                         : 30  ; /* [31:2] */
        unsigned int    reg_deskew_numlock_err_rcv_mask : 1  ; /* [1] */
        unsigned int    reg_symbol_numlock_err_rcv_mask : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_MAC_DESKEW_SYMBOL_UNLOCK_RCV_MASK;

/* Define the union U_MAC_REG_GEN4_EQ_OPT_TX_PRESET_1 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    opt_gen4_preset_1 : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_MAC_REG_GEN4_EQ_OPT_TX_PRESET_1;

/* Define the union U_MAC_REG_GEN4_EQ_OPT_TX_PRESET_2 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    opt_gen4_preset_2 : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_MAC_REG_GEN4_EQ_OPT_TX_PRESET_2;

/* Define the union U_MAC_REG_LP_GEN4_TX_PRESET_P1_1 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    lp_gen4_tx_preset_p1_1 : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_MAC_REG_LP_GEN4_TX_PRESET_P1_1;

/* Define the union U_MAC_REG_LP_GEN4_TX_PRESET_P1_2 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    lp_gen4_tx_preset_p1_2 : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_MAC_REG_LP_GEN4_TX_PRESET_P1_2;

/* Define the union U_MAC_LPBK_DATA */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    reg_lpbk_data : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_MAC_LPBK_DATA;

/* Define the union U_MAC_RX_MARGIN_SELF_CTRL */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_165                : 30  ; /* [31:2] */
        unsigned int    reg_dfe_cfg_value      : 1  ; /* [1] */
        unsigned int    reg_dfe_disable_cfg_en : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_MAC_RX_MARGIN_SELF_CTRL;

/* Define the union U_MAC_RX_MARGIN_CFG */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    reg_margin_global_disable            : 1  ; /* [31] */
        unsigned int    rsv_166                              : 15  ; /* [30:16] */
        unsigned int    reg_margin_vender_define_cmd_payload : 8  ; /* [15:8] */
        unsigned int    rsv_167                              : 8  ; /* [7:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_MAC_RX_MARGIN_CFG;

/* Define the union U_GEN4_RX_MARGIN_CPA0 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_168                      : 1  ; /* [31] */
        unsigned int    max_voltage_offset           : 7  ; /* [30:24] */
        unsigned int    num_voltage_steps            : 8  ; /* [23:16] */
        unsigned int    rsv_169                      : 1  ; /* [15] */
        unsigned int    ind_up_down_voltage_support  : 1  ; /* [14] */
        unsigned int    max_timing_offset            : 6  ; /* [13:8] */
        unsigned int    voltage_support              : 1  ; /* [7] */
        unsigned int    indleft_right_timing_support : 1  ; /* [6] */
        unsigned int    num_timing_steps             : 6  ; /* [5:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_GEN4_RX_MARGIN_CPA0;

/* Define the union U_GEN4_RX_MARGIN_CPA1 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    sample_rate_voltage     : 6  ; /* [31:26] */
        unsigned int    rsv_170                 : 2  ; /* [25:24] */
        unsigned int    sample_reporting_method : 1  ; /* [23] */
        unsigned int    ind_error_sample        : 1  ; /* [22] */
        unsigned int    sample_rate_timing      : 6  ; /* [21:16] */
        unsigned int    rsv_171                 : 4  ; /* [15:12] */
        unsigned int    max_lane_support        : 5  ; /* [11:7] */
        unsigned int    rsv_172                 : 7  ; /* [6:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_GEN4_RX_MARGIN_CPA1;

/* Define the union U_GEN4_RX_MARGIN_RSV */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rx_margin_rsv : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_GEN4_RX_MARGIN_RSV;

/* Define the union U_MAC_REG_GEN3_EQ_FIX_TX_PRESET_1 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    reg_fix_8g_tx_preset_value1 : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_MAC_REG_GEN3_EQ_FIX_TX_PRESET_1;

/* Define the union U_MAC_REG_GEN3_EQ_FIX_TX_PRESET_2 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    reg_fix_8g_tx_preset_value2 : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_MAC_REG_GEN3_EQ_FIX_TX_PRESET_2;

/* Define the union U_MAC_REG_GEN4_EQ_FIX_TX_PRESET_1 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    reg_fix_16g_tx_preset_value1 : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_MAC_REG_GEN4_EQ_FIX_TX_PRESET_1;

/* Define the union U_MAC_REG_GEN4_EQ_FIX_TX_PRESET_2 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    reg_fix_16g_tx_preset_value2 : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_MAC_REG_GEN4_EQ_FIX_TX_PRESET_2;

/* Define the union U_MAC_REG_PHASE01_COARSETUNE_START_TM_VALUE */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    resvered                            : 13  ; /* [31:19] */
        unsigned int    reg_up_16g_phase1_hold_en           : 1  ; /* [18] */
        unsigned int    reg_up_8g_phase1_hold_en            : 1  ; /* [17] */
        unsigned int    reg_16g_phase01_timeout_skip_en     : 1  ; /* [16] */
        unsigned int    reg_8g_phase01_timeout_skip_en      : 1  ; /* [15] */
        unsigned int    reg_16g_ignore_ctle_done            : 1  ; /* [14] */
        unsigned int    reg_8g_ignore_ctle_done             : 1  ; /* [13] */
        unsigned int    reg_coarsetune_start_use_rxvalid_en : 1  ; /* [12] */
        unsigned int    reg_coarsetune_start_use_rxidle_en  : 1  ; /* [11] */
        unsigned int    reg_phase01_coarsetune_start_tm     : 11  ; /* [10:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_MAC_REG_PHASE01_COARSETUNE_START_TM_VALUE;

/* Define the union U_MAC_LTSSM_TIMEOUT_ENABLE */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    resvered             : 24  ; /* [31:8] */
        unsigned int    reg_ltssm_timeout_en : 8  ; /* [7:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_MAC_LTSSM_TIMEOUT_ENABLE;

/* Define the union U_MAC_LOOPBACK_EC_VALUE */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    loopback_ec_value : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_MAC_LOOPBACK_EC_VALUE;

/* Define the union U_MAC_LANE_REVERSE_CFG */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    resver                      : 20  ; /* [31:12] */
        unsigned int    lane0_number                : 4  ; /* [11:8] */
        unsigned int    resvered                    : 1  ; /* [7] */
        unsigned int    reg_unused_lane_turn_off_en : 1  ; /* [6] */
        unsigned int    reg_compliance_mode         : 1  ; /* [5] */
        unsigned int    reg_lane_reverse_mux_cfg_en : 1  ; /* [4] */
        unsigned int    reg_lane_reverse_mux_value  : 4  ; /* [3:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_MAC_LANE_REVERSE_CFG;

/* Define the union U_MAC_PIPE_SRIS_EN */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    resvered            : 16  ; /* [31:16] */
        unsigned int    reg_mac2phy_sris_en : 16  ; /* [15:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_MAC_PIPE_SRIS_EN;

/* Define the union U_MAC_PIPE_EBUF_MODE */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    resvered              : 16  ; /* [31:16] */
        unsigned int    reg_mac2phy_ebuf_mode : 16  ; /* [15:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_MAC_PIPE_EBUF_MODE;

/* Define the union U_MAC_PIPE_SRIS_EN0 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    reg_ebuff_depth03 : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_MAC_PIPE_SRIS_EN0;

/* Define the union U_MAC_PIPE_SRIS_EN1 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    reg_ebuff_depth47 : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_MAC_PIPE_SRIS_EN1;

/* Define the union U_MAC_PIPE_SRIS_EN2 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    reg_ebuff_depth811 : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_MAC_PIPE_SRIS_EN2;

/* Define the union U_MAC_PIPE_SRIS_EN3 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    reg_ebuff_depth1216 : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_MAC_PIPE_SRIS_EN3;

/* Define the union U_MAC_FRAMING_ERR_CNT */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    resvered              : 16  ; /* [31:16] */
        unsigned int    reg_framing_err_count : 16  ; /* [15:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_MAC_FRAMING_ERR_CNT;

/* Define the union U_MAC_FRAMING_ERR_CTRL */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    resvered                      : 16  ; /* [31:16] */
        unsigned int    reg_framing_mask              : 8  ; /* [15:8] */
        unsigned int    rsv_173                       : 5  ; /* [7:3] */
        unsigned int    reg_pcs_decode_err_retrain_en : 1  ; /* [2] */
        unsigned int    reg_framing_err_rpt_en        : 1  ; /* [1] */
        unsigned int    reg_framing_err_retrain_en    : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_MAC_FRAMING_ERR_CTRL;

/* Define the union U_MAC_LINKDOWN_REQ_MASK */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    resvered                  : 29  ; /* [31:3] */
        unsigned int    reg_mac_linkdown_req_mask : 3  ; /* [2:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_MAC_LINKDOWN_REQ_MASK;

/* Define the union U_MAC_INT_TYPE_SEL */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    resvered             : 1  ; /* [31] */
        unsigned int    reg_mac_int_type_sel : 31  ; /* [30:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_MAC_INT_TYPE_SEL;

/* Define the union U_MAC_REQ_COEFF_INFO */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    resvered           : 4  ; /* [31:28] */
        unsigned int    tx_preset          : 4  ; /* [27:24] */
        unsigned int    rsv_174            : 2  ; /* [23:22] */
        unsigned int    req_pre_cur_coeff  : 6  ; /* [21:16] */
        unsigned int    rsv_175            : 2  ; /* [15:14] */
        unsigned int    req_cur_coeff      : 6  ; /* [13:8] */
        unsigned int    fig_merit_feedback : 8  ; /* [7:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_MAC_REQ_COEFF_INFO;

/* Define the union U_MAC_RX_COEFF_INFO */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    resvered          : 4  ; /* [31:28] */
        unsigned int    rx_xmt_preset     : 4  ; /* [27:24] */
        unsigned int    rsv_176           : 2  ; /* [23:22] */
        unsigned int    rx_pre_cur_coeff  : 6  ; /* [21:16] */
        unsigned int    rsv_177           : 2  ; /* [15:14] */
        unsigned int    rx_cur_coeff      : 6  ; /* [13:8] */
        unsigned int    rsv_178           : 1  ; /* [7] */
        unsigned int    rx_use_preset     : 1  ; /* [6] */
        unsigned int    rx_post_cur_coeff : 6  ; /* [5:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_MAC_RX_COEFF_INFO;

/* Define the union U_MAC_LEAVE_L0_INFO */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    resvered                : 12  ; /* [31:20] */
        unsigned int    rcv_eios                : 1  ; /* [19] */
        unsigned int    enter_l1l2_timeout      : 1  ; /* [18] */
        unsigned int    enter_l0s_req           : 1  ; /* [17] */
        unsigned int    enter_l1_req            : 1  ; /* [16] */
        unsigned int    enter_l2_req            : 1  ; /* [15] */
        unsigned int    dl_req_link_down        : 1  ; /* [14] */
        unsigned int    tl_ap_req_link_down     : 1  ; /* [13] */
        unsigned int    direct_speed_change     : 1  ; /* [12] */
        unsigned int    det_ts_train            : 1  ; /* [11] */
        unsigned int    det_eieos_128b130b      : 1  ; /* [10] */
        unsigned int    reg_retrain_req         : 1  ; /* [9] */
        unsigned int    cfg_retrain_req         : 1  ; /* [8] */
        unsigned int    hot_reset               : 1  ; /* [7] */
        unsigned int    skp_infter_idle_timeout : 1  ; /* [6] */
        unsigned int    dl_retran               : 1  ; /* [5] */
        unsigned int    framing_err_retrain     : 1  ; /* [4] */
        unsigned int    enter_loop_back         : 1  ; /* [3] */
        unsigned int    cfg_link_disable        : 1  ; /* [2] */
        unsigned int    dp_redp_eq_enter_rcv    : 1  ; /* [1] */
        unsigned int    up_retrain_redo_req     : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_MAC_LEAVE_L0_INFO;

/* Define the union U_MAC_GEN4_LOW_SKP_CFG */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    resver                  : 7  ; /* [31:25] */
        unsigned int    reg_skp_intvl_srns_gen4 : 9  ; /* [24:16] */
        unsigned int    resvered                : 7  ; /* [15:9] */
        unsigned int    reg_skp_intvl_sris_gen4 : 9  ; /* [8:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_MAC_GEN4_LOW_SKP_CFG;

/* Define the union U_DFX_APB_LANE_ERROR_STATUS_0 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    pcs_rcv_err_status       : 16  ; /* [31:16] */
        unsigned int    symbol_unlock_err_status : 16  ; /* [15:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_DFX_APB_LANE_ERROR_STATUS_0;

/* Define the union U_DFX_APB_LANE_ERROR_STATUS_1 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    loopback_link_data_err_status : 16  ; /* [31:16] */
        unsigned int    phy_lane_err_status           : 16  ; /* [15:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_DFX_APB_LANE_ERROR_STATUS_1;

/* Define the union U_REG_FIX_LP_8G_TX_COEFF */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    reg_8g_eq_fix_lp_tx_use_preset : 1  ; /* [31] */
        unsigned int    resvered                       : 13  ; /* [30:18] */
        unsigned int    reg_8g_eq_fix_lp_tx_coeff      : 18  ; /* [17:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_REG_FIX_LP_8G_TX_COEFF;

/* Define the union U_REG_FIX_LP_16G_TX_COEFF */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    reg_16g_eq_fix_lp_tx_use_preset : 1  ; /* [31] */
        unsigned int    resvered                        : 13  ; /* [30:18] */
        unsigned int    reg_16g_eq_fix_lp_tx_coeff      : 18  ; /* [17:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_REG_FIX_LP_16G_TX_COEFF;

/* Define the union U_REG_RXIDLE_DELAY_TIME */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    resvered                 : 24  ; /* [31:8] */
        unsigned int    reg_rxeleidle_delay_time : 8  ; /* [7:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_REG_RXIDLE_DELAY_TIME;

/* Define the union U_MAC_REG_16G_PHY_EQ_FB_SEL */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_179                  : 16  ; /* [31:16] */
        unsigned int    reg_up_8g_eqts2_sent_en  : 1  ; /* [15] */
        unsigned int    cfg_16g_reset_eieos      : 1  ; /* [14] */
        unsigned int    cfg_16g_merit_step       : 6  ; /* [13:8] */
        unsigned int    rsv_180                  : 2  ; /* [7:6] */
        unsigned int    reg_16g_coeff_search_len : 4  ; /* [5:2] */
        unsigned int    reg_16g_phy_eq_fb_sel    : 2  ; /* [1:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_MAC_REG_16G_PHY_EQ_FB_SEL;

/* Define the union U_MAC_REG_TX_MARGIN_CTRL */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_181                  : 27  ; /* [31:5] */
        unsigned int    reg_tx_margin_mask       : 1  ; /* [4] */
        unsigned int    rsv_182                  : 1  ; /* [3] */
        unsigned int    reg_tx_margin_mask_value : 3  ; /* [2:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_MAC_REG_TX_MARGIN_CTRL;

/* Define the union U_MAC_REG_UP_8GT_EQTS2_PRESET_0 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    reg_up_8gt_eqts2_preset_0 : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_MAC_REG_UP_8GT_EQTS2_PRESET_0;

/* Define the union U_MAC_REG_UP_8GT_EQTS2_PRESET_1 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    reg_up_8gt_eqts2_preset_1 : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_MAC_REG_UP_8GT_EQTS2_PRESET_1;

/* Define the union U_REG_RXVALID_DELAY_TIME */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    resvered               : 24  ; /* [31:8] */
        unsigned int    reg_rxvalid_delay_time : 8  ; /* [7:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_REG_RXVALID_DELAY_TIME;


//==============================================================================
/* Define the global struct */
typedef struct
{
    volatile U_MAC_REQ_EIOS_TO_ELEIDLE_DELAY             MAC_REQ_EIOS_TO_ELEIDLE_DELAY             ; /* 0 */
    volatile U_MAC_REG_ENTER_LOOPBACK                    MAC_REG_ENTER_LOOPBACK                    ; /* 4 */
    volatile U_MAC_REG_RETRAIN_LINK                      MAC_REG_RETRAIN_LINK                      ; /* 8 */
    volatile U_MAC_REQ_TX_LINK_NUM                       MAC_REQ_TX_LINK_NUM                       ; /* C */
    volatile U_MAC_REQ_SCRAMBLE_DISABLE                  MAC_REQ_SCRAMBLE_DISABLE                  ; /* 10 */
    volatile U_MAC_REG_SKP_INTVAL_SRIS                   MAC_REG_SKP_INTVAL_SRIS                   ; /* 14 */
    volatile U_MAC_REG_DC_BALANCE_DISABLE                MAC_REG_DC_BALANCE_DISABLE                ; /* 18 */
    volatile U_MAC_REG_EQ_DISABLE                        MAC_REG_EQ_DISABLE                        ; /* 1C */
    volatile U_MAC_REG_SUPPORTED_TX_PRESET_BM            MAC_REG_SUPPORTED_TX_PRESET_BM            ; /* 20 */
    volatile U_MAC_REG_8G_PHY_EQ_FB_SEL                  MAC_REG_8G_PHY_EQ_FB_SEL                  ; /* 24 */
    volatile U_MAC_REG_GEN3_TX_COEFF_MAP_MODE            MAC_REG_GEN3_TX_COEFF_MAP_MODE            ; /* 28 */
    volatile U_MAC_REG_EQ_PHASE23_CONV_STEP_ADDR         MAC_REG_EQ_PHASE23_CONV_STEP_ADDR         ; /* 2C */
    volatile U_MAC_REG_EQ_PHASE23_TIMEOUT_VAL            MAC_REG_EQ_PHASE23_TIMEOUT_VAL            ; /* 30 */
    volatile U_MAC_REG_SKP_INTVAL_SRNS                   MAC_REG_SKP_INTVAL_SRNS                   ; /* 34 */
    volatile U_MAC_REG_N_FTS                             MAC_REG_N_FTS                             ; /* 38 */
    volatile U_MAC_REG_PHYSTATUS_DET_TIMEOUT_VAL         MAC_REG_PHYSTATUS_DET_TIMEOUT_VAL         ; /* 3C */
    volatile U_MAC_REG_RDN_CROSS_TIMEOUT_VAL             MAC_REG_RDN_CROSS_TIMEOUT_VAL             ; /* 40 */
    volatile U_MAC_REG_SEL_DEEMPH_US                     MAC_REG_SEL_DEEMPH_US                     ; /* 44 */
    volatile U_MAC_REG_TX_COMP_RCV                       MAC_REG_TX_COMP_RCV                       ; /* 48 */
    volatile U_MAC_REG_TXSWING                           MAC_REG_TXSWING                           ; /* 4C */
    volatile U_MAC_REG_LTSSM_TRACER_INPUT                MAC_REG_LTSSM_TRACER_INPUT                ; /* 50 */
    volatile U_MAC_REG_MAC_INT_STATUS                    MAC_REG_MAC_INT_STATUS                    ; /* 54 */
    volatile U_MAC_REG_MAC_INT_MASK                      MAC_REG_MAC_INT_MASK                      ; /* 58 */
    volatile U_MAC_REG_TEST_COUNTER                      MAC_REG_TEST_COUNTER                      ; /* 5C */
    volatile U_MAC_REG_LINK_INFO                         MAC_REG_LINK_INFO                         ; /* 60 */
    volatile U_MAC_REG_DEBUG_PIPE1                       MAC_REG_DEBUG_PIPE1                       ; /* 64 */
    volatile U_MAC_REG_DEBUG_PIPE2                       MAC_REG_DEBUG_PIPE2                       ; /* 68 */
    volatile U_MAC_REG_DEBUG_PIPE3                       MAC_REG_DEBUG_PIPE3                       ; /* 6C */
    volatile U_MAC_REG_DEBUG_PIPE4                       MAC_REG_DEBUG_PIPE4                       ; /* 70 */
    volatile U_MAC_REG_DEBUG_RXDLI_1                     MAC_REG_DEBUG_RXDLI_1                     ; /* 74 */
    volatile U_MAC_REG_DEBUG_LINK_NUM_1                  MAC_REG_DEBUG_LINK_NUM_1                  ; /* 78 */
    volatile U_MAC_REG_DEBUG_LANE_NUM_1                  MAC_REG_DEBUG_LANE_NUM_1                  ; /* 7C */
    volatile U_MAC_REG_DEBUG_TXDLI                       MAC_REG_DEBUG_TXDLI                       ; /* 80 */
    volatile U_MAC_REG_LTSSM_TRACER_OUTPUT_1             MAC_REG_LTSSM_TRACER_OUTPUT_1             ; /* 84 */
    volatile U_MAC_REG_LTSSM_TRACER_LAST_ADDR            MAC_REG_LTSSM_TRACER_LAST_ADDR            ; /* 88 */
    volatile U_MAC_REG_SYMBOL_UNLOCL_COUNTER             MAC_REG_SYMBOL_UNLOCL_COUNTER             ; /* 8C */
    volatile U_MAC_REG_MAC_INT_RO                        MAC_REG_MAC_INT_RO                        ; /* 90 */
    volatile U_MAC_REG_MAC_INT_SET                       MAC_REG_MAC_INT_SET                       ; /* 94 */
    volatile U_MAC_REG_ENTER_L1L2_TIMEOUT_VAL            MAC_REG_ENTER_L1L2_TIMEOUT_VAL            ; /* 98 */
    volatile U_MAC_REG_EQ_FIX_LP_TX_PRESET               MAC_REG_EQ_FIX_LP_TX_PRESET               ; /* 9C */
    volatile U_MAC_REG_ADJ_HILINK_MODE_EN                MAC_REG_ADJ_HILINK_MODE_EN                ; /* A0 */
    volatile U_MAC_REG_LP_GEN3_TX_PRESET_P1_1            MAC_REG_LP_GEN3_TX_PRESET_P1_1            ; /* A4 */
    volatile U_MAC_REG_EQ_OPT_TX_PRESET_1                MAC_REG_EQ_OPT_TX_PRESET_1                ; /* A8 */
    volatile U_MAC_REG_LOOPBACK_PRESET_TIMEOUT_VAL_ADDR  MAC_REG_LOOPBACK_PRESET_TIMEOUT_VAL_ADDR  ; /* AC */
    volatile U_MAC_REG_COMP_OPTION                       MAC_REG_COMP_OPTION                       ; /* B0 */
    volatile U_MAC_REG_PHY_RXDATA_TS                     MAC_REG_PHY_RXDATA_TS                     ; /* B4 */
    volatile U_MAC_REG_ECO_RSV0                          MAC_REG_ECO_RSV0                          ; /* B8 */
    volatile U_MAC_REG_ECO_RSV1                          MAC_REG_ECO_RSV1                          ; /* BC */
    volatile U_MAC_REGEQ_TRACE                           MAC_REGEQ_TRACE                           ; /* C0 */
    volatile U_MAC_REG_EQ_TIMEOUT_SET                    MAC_REG_EQ_TIMEOUT_SET                    ; /* C4 */
    volatile U_MAC_REG_EQ_INIT_COEFF_CFG                 MAC_REG_EQ_INIT_COEFF_CFG                 ; /* C8 */
    volatile U_MAC_REG_WAIT_LINK_NUM_TIMER               MAC_REG_WAIT_LINK_NUM_TIMER               ; /* CC */
    volatile U_MAC_REG_LANE_COEFF_1                      MAC_REG_LANE_COEFF_1[8]                   ; /* 100 */
    volatile U_MAC_REG_PRESET0                           MAC_REG_PRESET0                           ; /* 200 */
    volatile U_MAC_REG_PRESET1                           MAC_REG_PRESET1                           ; /* 204 */
    volatile U_MAC_REG_PRESET2                           MAC_REG_PRESET2                           ; /* 208 */
    volatile U_MAC_REG_PRESET3                           MAC_REG_PRESET3                           ; /* 20C */
    volatile U_MAC_REG_PRESET4                           MAC_REG_PRESET4                           ; /* 210 */
    volatile U_MAC_REG_PRESET5                           MAC_REG_PRESET5                           ; /* 214 */
    volatile U_MAC_REG_PRESET6                           MAC_REG_PRESET6                           ; /* 218 */
    volatile U_MAC_REG_PRESET7                           MAC_REG_PRESET7                           ; /* 21C */
    volatile U_MAC_REG_PRESET8                           MAC_REG_PRESET8                           ; /* 220 */
    volatile U_MAC_REG_PRESET9                           MAC_REG_PRESET9                           ; /* 224 */
    volatile U_MAC_REG_PRESET10                          MAC_REG_PRESET10                          ; /* 228 */
    volatile U_MAC_REG_PRESET11                          MAC_REG_PRESET11                          ; /* 22C */
    volatile U_MAC_REG_PRESET12                          MAC_REG_PRESET12                          ; /* 230 */
    volatile U_MAC_REG_PRESET13                          MAC_REG_PRESET13                          ; /* 234 */
    volatile U_MAC_REG_PRESET14                          MAC_REG_PRESET14                          ; /* 238 */
    volatile U_MAC_REG_PRESET15                          MAC_REG_PRESET15                          ; /* 23C */
    volatile U_MAC_REG_DEBUG_PIPE5                       MAC_REG_DEBUG_PIPE5                       ; /* 240 */
    volatile U_MAC_REG_DEBUG_PIPE6                       MAC_REG_DEBUG_PIPE6                       ; /* 244 */
    volatile U_MAC_REG_DEBUG_PIPE7                       MAC_REG_DEBUG_PIPE7                       ; /* 248 */
    volatile U_MAC_REG_DEBUG_PIPE8                       MAC_REG_DEBUG_PIPE8                       ; /* 24C */
    volatile U_MAC_REG_DEBUG_PIPE9                       MAC_REG_DEBUG_PIPE9                       ; /* 250 */
    volatile U_MAC_REG_DEBUG_PIPE10                      MAC_REG_DEBUG_PIPE10                      ; /* 254 */
    volatile U_MAC_REG_DEBUG_PIPE11                      MAC_REG_DEBUG_PIPE11                      ; /* 258 */
    volatile U_MAC_REG_DEBUG_RXDLI_2                     MAC_REG_DEBUG_RXDLI_2                     ; /* 25C */
    volatile U_MAC_REG_DEBUG_LINK_NUM_2                  MAC_REG_DEBUG_LINK_NUM_2                  ; /* 260 */
    volatile U_MAC_REG_DEBUG_LINK_NUM_3                  MAC_REG_DEBUG_LINK_NUM_3                  ; /* 264 */
    volatile U_MAC_REG_DEBUG_LINK_NUM_4                  MAC_REG_DEBUG_LINK_NUM_4                  ; /* 268 */
    volatile U_MAC_REG_DEBUG_LANE_NUM_2                  MAC_REG_DEBUG_LANE_NUM_2                  ; /* 26C */
    volatile U_MAC_REG_DEBUG_LANE_NUM_3                  MAC_REG_DEBUG_LANE_NUM_3                  ; /* 270 */
    volatile U_MAC_REG_DEBUG_LANE_NUM_4                  MAC_REG_DEBUG_LANE_NUM_4                  ; /* 274 */
    volatile U_MAC_REG_LP_GEN3_TX_PRESET_P1_2            MAC_REG_LP_GEN3_TX_PRESET_P1_2            ; /* 278 */
    volatile U_MAC_REG_GEN3_EQ_OPT_TX_PRESET_2           MAC_REG_GEN3_EQ_OPT_TX_PRESET_2           ; /* 27C */
    volatile U_MAC_REG_LANE_COEFF_2                      MAC_REG_LANE_COEFF_2[8]                   ; /* 280 */
    volatile U_MAC_REG_LTSSM_TRACER_OUTPUT_2             MAC_REG_LTSSM_TRACER_OUTPUT_2             ; /* 2A0 */
    volatile U_MAC_REG_LTSSM_TRACER_OUTPUT_OK            MAC_REG_LTSSM_TRACER_OUTPUT_OK            ; /* 2A4 */
    volatile U_MAC_REG_LTSSM_TRACER_SRAM_ECC_INSERT      MAC_REG_LTSSM_TRACER_SRAM_ECC_INSERT      ; /* 2A8 */
    volatile U_MAC_REG_LTSSM_TRACER_ECC_ERR_ADDR         MAC_REG_LTSSM_TRACER_ECC_ERR_ADDR         ; /* 2AC */
    volatile U_MAC_REG_COEFF_SEARCH_TRACER_OUTPUT        MAC_REG_COEFF_SEARCH_TRACER_OUTPUT        ; /* 2B0 */
    volatile U_MAC_REG_REMOTE_FS_LF                      MAC_REG_REMOTE_FS_LF                      ; /* 2B4 */
    volatile U_MAC_LOOP_LINK_DATA_ERR_COUNT              MAC_LOOP_LINK_DATA_ERR_COUNT              ; /* 2B8 */
    volatile U_MAC_PCS_RX_ERR_CNT                        MAC_PCS_RX_ERR_CNT                        ; /* 2BC */
    volatile U_MAC_UP_MAX_AUTO_REDO_NUM                  MAC_UP_MAX_AUTO_REDO_NUM                  ; /* 2C0 */
    volatile U_MAC_WAIT_LANE_NUM_TIMER                   MAC_WAIT_LANE_NUM_TIMER                   ; /* 2C4 */
    volatile U_MAC_LANE_NUM_WAIT_TIMER                   MAC_LANE_NUM_WAIT_TIMER                   ; /* 2C8 */
    volatile U_MAC_LANE_NUM_ACC_TIMER                    MAC_LANE_NUM_ACC_TIMER                    ; /* 2CC */
    volatile U_MAC_LNW_TO_LNA_1MS_TIMER                  MAC_LNW_TO_LNA_1MS_TIMER                  ; /* 2D0 */
    volatile U_MAC_EQ_LTSMM_HOLD_TIMER                   MAC_EQ_LTSMM_HOLD_TIMER                   ; /* 2D4 */
    volatile U_MAC_LTSSM_CRTL_INFER_ELECIDLE             MAC_LTSSM_CRTL_INFER_ELECIDLE             ; /* 2D8 */
    volatile U_MAC_LTSSM_TRACER_CFG0                     MAC_LTSSM_TRACER_CFG0                     ; /* 2DC */
    volatile U_MAC_LTSSM_TRACER_CFG1                     MAC_LTSSM_TRACER_CFG1                     ; /* 2E0 */
    volatile U_MAC_CMP_LOOP_SENT_EQTS1                   MAC_CMP_LOOP_SENT_EQTS1                   ; /* 2E8 */
    volatile U_MAC_ENTER_LPBK_DISABLE                    MAC_ENTER_LPBK_DISABLE                    ; /* 2EC */
    volatile U_MAC_PRESET_TABLE0                         MAC_PRESET_TABLE0                         ; /* 2F0 */
    volatile U_MAC_PRESET_TABLE1                         MAC_PRESET_TABLE1                         ; /* 2F4 */
    volatile U_MAC_REG_LTSSM_TRACERADDR                  MAC_REG_LTSSM_TRACERADDR                  ; /* 2F8 */
    volatile U_MAC_CFG_COMPLETE_TIMER                    MAC_CFG_COMPLETE_TIMER                    ; /* 2FC */
    volatile U_MAC_CFG_COMP_ERRATA_DISABLE               MAC_CFG_COMP_ERRATA_DISABLE               ; /* 300 */
    volatile U_MAC_RX_ERR_CHECK_EN                       MAC_RX_ERR_CHECK_EN                       ; /* 304 */
    volatile U_MAC_TRACE_2BIT_ECC_CNT                    MAC_TRACE_2BIT_ECC_CNT                    ; /* 308 */
    volatile U_MAC_TRACE_1BIT_ECC_CNT                    MAC_TRACE_1BIT_ECC_CNT                    ; /* 30C */
    volatile U_MAC_CFG_RCV_HOLD_EN                       MAC_CFG_RCV_HOLD_EN                       ; /* 310 */
    volatile U_MAC_CFG_RCV_LOCK_HOLD_TIME                MAC_CFG_RCV_LOCK_HOLD_TIME                ; /* 314 */
    volatile U_MAC_CFG_RCV_CFG_HOLD_TIME                 MAC_CFG_RCV_CFG_HOLD_TIME                 ; /* 318 */
    volatile U_MAC_CFG_RCV_IDLE_HOLD_TIME                MAC_CFG_RCV_IDLE_HOLD_TIME                ; /* 31C */
    volatile U_MAC_LTSSM_INT_STATUS                      MAC_LTSSM_INT_STATUS                      ; /* 320 */
    volatile U_MAC_DESKEW_SYMBOL_UNLOCK_RCV_MASK         MAC_DESKEW_SYMBOL_UNLOCK_RCV_MASK         ; /* 324 */
    volatile U_MAC_REG_GEN4_EQ_OPT_TX_PRESET_1           MAC_REG_GEN4_EQ_OPT_TX_PRESET_1           ; /* 328 */
    volatile U_MAC_REG_GEN4_EQ_OPT_TX_PRESET_2           MAC_REG_GEN4_EQ_OPT_TX_PRESET_2           ; /* 32C */
    volatile U_MAC_REG_LP_GEN4_TX_PRESET_P1_1            MAC_REG_LP_GEN4_TX_PRESET_P1_1            ; /* 330 */
    volatile U_MAC_REG_LP_GEN4_TX_PRESET_P1_2            MAC_REG_LP_GEN4_TX_PRESET_P1_2            ; /* 334 */
    volatile U_MAC_LPBK_DATA                             MAC_LPBK_DATA                             ; /* 338 */
    volatile U_MAC_RX_MARGIN_SELF_CTRL                   MAC_RX_MARGIN_SELF_CTRL                   ; /* 33C */
    volatile U_MAC_RX_MARGIN_CFG                         MAC_RX_MARGIN_CFG                         ; /* 340 */
    volatile U_GEN4_RX_MARGIN_CPA0                       GEN4_RX_MARGIN_CPA0                       ; /* 344 */
    volatile U_GEN4_RX_MARGIN_CPA1                       GEN4_RX_MARGIN_CPA1                       ; /* 348 */
    volatile U_GEN4_RX_MARGIN_RSV                        GEN4_RX_MARGIN_RSV                        ; /* 34C */
    volatile U_MAC_REG_GEN3_EQ_FIX_TX_PRESET_1           MAC_REG_GEN3_EQ_FIX_TX_PRESET_1           ; /* 350 */
    volatile U_MAC_REG_GEN3_EQ_FIX_TX_PRESET_2           MAC_REG_GEN3_EQ_FIX_TX_PRESET_2           ; /* 354 */
    volatile U_MAC_REG_GEN4_EQ_FIX_TX_PRESET_1           MAC_REG_GEN4_EQ_FIX_TX_PRESET_1           ; /* 358 */
    volatile U_MAC_REG_GEN4_EQ_FIX_TX_PRESET_2           MAC_REG_GEN4_EQ_FIX_TX_PRESET_2           ; /* 35C */
    volatile U_MAC_REG_PHASE01_COARSETUNE_START_TM_VALUE MAC_REG_PHASE01_COARSETUNE_START_TM_VALUE ; /* 360 */
    volatile U_MAC_LTSSM_TIMEOUT_ENABLE                  MAC_LTSSM_TIMEOUT_ENABLE                  ; /* 364 */
    volatile U_MAC_LOOPBACK_EC_VALUE                     MAC_LOOPBACK_EC_VALUE                     ; /* 368 */
    volatile U_MAC_LANE_REVERSE_CFG                      MAC_LANE_REVERSE_CFG                      ; /* 36C */
    volatile U_MAC_PIPE_SRIS_EN                          MAC_PIPE_SRIS_EN                          ; /* 370 */
    volatile U_MAC_PIPE_EBUF_MODE                        MAC_PIPE_EBUF_MODE                        ; /* 374 */
    volatile U_MAC_PIPE_SRIS_EN0                         MAC_PIPE_SRIS_EN0                         ; /* 378 */
    volatile U_MAC_PIPE_SRIS_EN1                         MAC_PIPE_SRIS_EN1                         ; /* 37C */
    volatile U_MAC_PIPE_SRIS_EN2                         MAC_PIPE_SRIS_EN2                         ; /* 380 */
    volatile U_MAC_PIPE_SRIS_EN3                         MAC_PIPE_SRIS_EN3                         ; /* 384 */
    volatile U_MAC_FRAMING_ERR_CNT                       MAC_FRAMING_ERR_CNT                       ; /* 39C */
    volatile U_MAC_FRAMING_ERR_CTRL                      MAC_FRAMING_ERR_CTRL                      ; /* 3A0 */
    volatile U_MAC_LINKDOWN_REQ_MASK                     MAC_LINKDOWN_REQ_MASK                     ; /* 3A4 */
    volatile U_MAC_INT_TYPE_SEL                          MAC_INT_TYPE_SEL                          ; /* 3A8 */
    volatile U_MAC_REQ_COEFF_INFO                        MAC_REQ_COEFF_INFO                        ; /* 3AC */
    volatile U_MAC_RX_COEFF_INFO                         MAC_RX_COEFF_INFO                         ; /* 3B0 */
    volatile U_MAC_LEAVE_L0_INFO                         MAC_LEAVE_L0_INFO                         ; /* 3B4 */
    volatile U_MAC_GEN4_LOW_SKP_CFG                      MAC_GEN4_LOW_SKP_CFG                      ; /* 3B8 */
    volatile U_DFX_APB_LANE_ERROR_STATUS_0               DFX_APB_LANE_ERROR_STATUS_0               ; /* 3BC */
    volatile U_DFX_APB_LANE_ERROR_STATUS_1               DFX_APB_LANE_ERROR_STATUS_1               ; /* 3C0 */
    volatile U_REG_FIX_LP_8G_TX_COEFF                    REG_FIX_LP_8G_TX_COEFF                    ; /* 3C4 */
    volatile U_REG_FIX_LP_16G_TX_COEFF                   REG_FIX_LP_16G_TX_COEFF                   ; /* 3C8 */
    volatile U_REG_RXIDLE_DELAY_TIME                     REG_RXIDLE_DELAY_TIME                     ; /* 3CC */
    volatile U_MAC_REG_16G_PHY_EQ_FB_SEL                 MAC_REG_16G_PHY_EQ_FB_SEL                 ; /* 3D0 */
    volatile U_MAC_REG_TX_MARGIN_CTRL                    MAC_REG_TX_MARGIN_CTRL                    ; /* 3D4 */
    volatile U_MAC_REG_UP_8GT_EQTS2_PRESET_0             MAC_REG_UP_8GT_EQTS2_PRESET_0             ; /* 3D8 */
    volatile U_MAC_REG_UP_8GT_EQTS2_PRESET_1             MAC_REG_UP_8GT_EQTS2_PRESET_1             ; /* 3DC */
    volatile U_REG_RXVALID_DELAY_TIME                    REG_RXVALID_DELAY_TIME                    ; /* 3E0 */

} S_hipciec_mac_reg_1_REGS_TYPE;

/* Declare the struct pointor of the module hipciec_mac_reg_1 */
extern volatile S_hipciec_mac_reg_1_REGS_TYPE *gophipciec_mac_reg_1AllReg;

/* Declare the functions that set the member value */
int iSetMAC_REQ_EIOS_TO_ELEIDLE_DELAY_reg_eios_to_eleidle_delay(unsigned int ureg_eios_to_eleidle_delay);
int iSetMAC_REG_ENTER_LOOPBACK_reg_loopback_wait_time(unsigned int ureg_loopback_wait_time);
int iSetMAC_REG_ENTER_LOOPBACK_mac_loc_preset_sigle(unsigned int umac_loc_preset_sigle);
int iSetMAC_REG_ENTER_LOOPBACK_enter_loop_con(unsigned int uenter_loop_con);
int iSetMAC_REG_ENTER_LOOPBACK_loopback_master_check_st(unsigned int uloopback_master_check_st);
int iSetMAC_REG_ENTER_LOOPBACK_dis_hotrst_sent_eieos_en(unsigned int udis_hotrst_sent_eieos_en);
int iSetMAC_REG_ENTER_LOOPBACK_reg_ds_l0_loopback_en(unsigned int ureg_ds_l0_loopback_en);
int iSetMAC_REG_ENTER_LOOPBACK_loopback_sent_eieos_en(unsigned int uloopback_sent_eieos_en);
int iSetMAC_REG_ENTER_LOOPBACK_reg_loopback_check_en(unsigned int ureg_loopback_check_en);
int iSetMAC_REG_ENTER_LOOPBACK_reg_enter_loopback(unsigned int ureg_enter_loopback);
int iSetMAC_REG_RETRAIN_LINK_max_dp_hw_req_redo_num(unsigned int umax_dp_hw_req_redo_num);
int iSetMAC_REG_RETRAIN_LINK_reg_req_tx_eq(unsigned int ureg_req_tx_eq);
int iSetMAC_REG_RETRAIN_LINK_reg_retrain_pulse(unsigned int ureg_retrain_pulse);
int iSetMAC_REQ_TX_LINK_NUM_reg_tx_link_num(unsigned int ureg_tx_link_num);
int iSetMAC_REQ_SCRAMBLE_DISABLE_reg_scramble_disable_gen3(unsigned int ureg_scramble_disable_gen3);
int iSetMAC_REQ_SCRAMBLE_DISABLE_reg_scramble_disable_gen12(unsigned int ureg_scramble_disable_gen12);
int iSetMAC_REG_SKP_INTVAL_SRIS_reg_skp_intvl_sris_gen3(unsigned int ureg_skp_intvl_sris_gen3);
int iSetMAC_REG_SKP_INTVAL_SRIS_reg_skp_intvl_sris_gen12(unsigned int ureg_skp_intvl_sris_gen12);
int iSetMAC_REG_DC_BALANCE_DISABLE_reg_dc_balance_disable(unsigned int ureg_dc_balance_disable);
int iSetMAC_REG_EQ_DISABLE_reg_ds_eq_p23_disable(unsigned int ureg_ds_eq_p23_disable);
int iSetMAC_REG_EQ_DISABLE_reg_equalization_disable(unsigned int ureg_equalization_disable);
int iSetMAC_REG_SUPPORTED_TX_PRESET_BM_reg_supported_tx_preset_bit_map(unsigned int ureg_supported_tx_preset_bit_map);
int iSetMAC_REG_8G_PHY_EQ_FB_SEL_cfg_8g_reset_eieos(unsigned int ucfg_8g_reset_eieos);
int iSetMAC_REG_8G_PHY_EQ_FB_SEL_cfg_8g_merit_step(unsigned int ucfg_8g_merit_step);
int iSetMAC_REG_8G_PHY_EQ_FB_SEL_reg_8g_coeff_search_len(unsigned int ureg_8g_coeff_search_len);
int iSetMAC_REG_8G_PHY_EQ_FB_SEL_reg_8g_phy_eq_fb_sel(unsigned int ureg_8g_phy_eq_fb_sel);
int iSetMAC_REG_GEN3_TX_COEFF_MAP_MODE_reg_gen3_tx_coeff_map_mode(unsigned int ureg_gen3_tx_coeff_map_mode);
int iSetMAC_REG_EQ_PHASE23_CONV_STEP_ADDR_reg_eq_phase23_conv_step(unsigned int ureg_eq_phase23_conv_step);
int iSetMAC_REG_EQ_PHASE23_TIMEOUT_VAL_reg_eq_phase3_timeout_val(unsigned int ureg_eq_phase3_timeout_val);
int iSetMAC_REG_EQ_PHASE23_TIMEOUT_VAL_reg_eq_phase2_timeout_val(unsigned int ureg_eq_phase2_timeout_val);
int iSetMAC_REG_SKP_INTVAL_SRNS_reg_skp_intvl_srns_gen3(unsigned int ureg_skp_intvl_srns_gen3);
int iSetMAC_REG_SKP_INTVAL_SRNS_reg_skp_intvl_srns_gen12(unsigned int ureg_skp_intvl_srns_gen12);
int iSetMAC_REG_N_FTS_reg_n_fts_gen3(unsigned int ureg_n_fts_gen3);
int iSetMAC_REG_N_FTS_reg_n_fts_gen2(unsigned int ureg_n_fts_gen2);
int iSetMAC_REG_N_FTS_reg_n_fts_gen1(unsigned int ureg_n_fts_gen1);
int iSetMAC_REG_PHYSTATUS_DET_TIMEOUT_VAL_reg_phystatus_det_timeout_val(unsigned int ureg_phystatus_det_timeout_val);
int iSetMAC_REG_RDN_CROSS_TIMEOUT_VAL_reg_random_cross_timeout_val(unsigned int ureg_random_cross_timeout_val);
int iSetMAC_REG_SEL_DEEMPH_US_reg_no_deemph(unsigned int ureg_no_deemph);
int iSetMAC_REG_SEL_DEEMPH_US_reg_sel_deemph_us(unsigned int ureg_sel_deemph_us);
int iSetMAC_REG_TX_COMP_RCV_reg_tx_compliance_rcv(unsigned int ureg_tx_compliance_rcv);
int iSetMAC_REG_TXSWING_reg_txswing(unsigned int ureg_txswing);
int iSetMAC_REG_LTSSM_TRACER_INPUT_reg_ltssm_tracer_cap_mode(unsigned int ureg_ltssm_tracer_cap_mode);
int iSetMAC_REG_LTSSM_TRACER_INPUT_reg_ltssm_tracer_recap(unsigned int ureg_ltssm_tracer_recap);
int iSetMAC_REG_MAC_INT_STATUS_reg_enter_g4_recovery_speed_intr_status(unsigned int ureg_enter_g4_recovery_speed_intr_status);
int iSetMAC_REG_MAC_INT_STATUS_reg_enter_lpbk_lock_intr_status(unsigned int ureg_enter_lpbk_lock_intr_status);
int iSetMAC_REG_MAC_INT_STATUS_reg_ltssm_intr_status(unsigned int ureg_ltssm_intr_status);
int iSetMAC_REG_MAC_INT_STATUS_reg_enter_g3_recovery_speed_intr_status(unsigned int ureg_enter_g3_recovery_speed_intr_status);
int iSetMAC_REG_MAC_INT_STATUS_reg_enter_g2_recovery_speed_intr_status(unsigned int ureg_enter_g2_recovery_speed_intr_status);
int iSetMAC_REG_MAC_INT_STATUS_reg_enter_g1_recovery_speed_intr_status(unsigned int ureg_enter_g1_recovery_speed_intr_status);
int iSetMAC_REG_MAC_INT_STATUS_ltssm_tracer_sram_ecc_2bit_err(unsigned int ultssm_tracer_sram_ecc_2bit_err);
int iSetMAC_REG_MAC_INT_STATUS_ltssm_tracer_sram_ecc_1bit_err(unsigned int ultssm_tracer_sram_ecc_1bit_err);
int iSetMAC_REG_MAC_INT_STATUS_pl_eco_rsv_intr_status(unsigned int upl_eco_rsv_intr_status);
int iSetMAC_REG_MAC_INT_STATUS_reg_enter_eq_p3_intr_status(unsigned int ureg_enter_eq_p3_intr_status);
int iSetMAC_REG_MAC_INT_STATUS_reg_enter_recovery_cfg_intr_status(unsigned int ureg_enter_recovery_cfg_intr_status);
int iSetMAC_REG_MAC_INT_STATUS_reg_enter_recovery_lock_intr_status(unsigned int ureg_enter_recovery_lock_intr_status);
int iSetMAC_REG_MAC_INT_STATUS_reg_enter_l2_timeout_intr_status(unsigned int ureg_enter_l2_timeout_intr_status);
int iSetMAC_REG_MAC_INT_STATUS_reg_enter_l1_timeout_intr_status(unsigned int ureg_enter_l1_timeout_intr_status);
int iSetMAC_REG_MAC_INT_STATUS_reg_deskew_fifo_overflow_intr_status(unsigned int ureg_deskew_fifo_overflow_intr_status);
int iSetMAC_REG_MAC_INT_STATUS_reg_loopback_unlock_intr_status(unsigned int ureg_loopback_unlock_intr_status);
int iSetMAC_REG_MAC_INT_STATUS_reg_symbol_unlock_intr_status(unsigned int ureg_symbol_unlock_intr_status);
int iSetMAC_REG_MAC_INT_STATUS_reg_deskew_unlock_intr_status(unsigned int ureg_deskew_unlock_intr_status);
int iSetMAC_REG_MAC_INT_STATUS_reg_phystatus_timeout_intr_status(unsigned int ureg_phystatus_timeout_intr_status);
int iSetMAC_REG_MAC_INT_STATUS_rxl0s_to_recovery_intr_status(unsigned int urxl0s_to_recovery_intr_status);
int iSetMAC_REG_MAC_INT_STATUS_reg_hot_reset_intr_status(unsigned int ureg_hot_reset_intr_status);
int iSetMAC_REG_MAC_INT_STATUS_reg_leave_disable_intr_status(unsigned int ureg_leave_disable_intr_status);
int iSetMAC_REG_MAC_INT_STATUS_reg_enter_disable_intr_status(unsigned int ureg_enter_disable_intr_status);
int iSetMAC_REG_MAC_INT_STATUS_reg_leave_l0_intr_status(unsigned int ureg_leave_l0_intr_status);
int iSetMAC_REG_MAC_INT_STATUS_reg_enter_l0_intr_status(unsigned int ureg_enter_l0_intr_status);
int iSetMAC_REG_MAC_INT_STATUS_reg_linkdown_intr_status(unsigned int ureg_linkdown_intr_status);
int iSetMAC_REG_MAC_INT_STATUS_reg_linkup_intr_status(unsigned int ureg_linkup_intr_status);
int iSetMAC_REG_MAC_INT_MASK_reg_intr_mask(unsigned int ureg_intr_mask);
int iSetMAC_REG_TEST_COUNTER_phy_lane_err_counter(unsigned int uphy_lane_err_counter);
int iSetMAC_REG_LINK_INFO_rx_deskew_st(unsigned int urx_deskew_st);
int iSetMAC_REG_LINK_INFO_mac_ltssm_st(unsigned int umac_ltssm_st);
int iSetMAC_REG_LINK_INFO_req_ending_txdata_en(unsigned int ureq_ending_txdata_en);
int iSetMAC_REG_LINK_INFO_lane_reverse(unsigned int ulane_reverse);
int iSetMAC_REG_LINK_INFO_mac_descramble_disable(unsigned int umac_descramble_disable);
int iSetMAC_REG_LINK_INFO_is_upstream_port_ltssm(unsigned int uis_upstream_port_ltssm);
int iSetMAC_REG_LINK_INFO_mac_link_up(unsigned int umac_link_up);
int iSetMAC_REG_LINK_INFO_rx_eval_st(unsigned int urx_eval_st);
int iSetMAC_REG_LINK_INFO_rxl0s_st(unsigned int urxl0s_st);
int iSetMAC_REG_LINK_INFO_mac_cur_link_speed(unsigned int umac_cur_link_speed);
int iSetMAC_REG_LINK_INFO_mac_cur_link_width(unsigned int umac_cur_link_width);
int iSetMAC_REG_DEBUG_PIPE1_mac_ltssm_st(unsigned int umac_ltssm_st);
int iSetMAC_REG_DEBUG_PIPE1_mac_txdetrx_loopbk(unsigned int umac_txdetrx_loopbk);
int iSetMAC_REG_DEBUG_PIPE2_mac_ltssm_st(unsigned int umac_ltssm_st);
int iSetMAC_REG_DEBUG_PIPE2_mac_powerdown_1(unsigned int umac_powerdown_1);
int iSetMAC_REG_DEBUG_PIPE3_mac_ltssm_st(unsigned int umac_ltssm_st);
int iSetMAC_REG_DEBUG_PIPE3_phy_phystatus(unsigned int uphy_phystatus);
int iSetMAC_REG_DEBUG_PIPE4_txdli_tx_buf_start(unsigned int utxdli_tx_buf_start);
int iSetMAC_REG_DEBUG_PIPE4_txdli_tx_buf_byte_cnt(unsigned int utxdli_tx_buf_byte_cnt);
int iSetMAC_REG_DEBUG_PIPE4_txdli_data_fifo_cnt(unsigned int utxdli_data_fifo_cnt);
int iSetMAC_REG_DEBUG_PIPE4_txdli_pkt_end(unsigned int utxdli_pkt_end);
int iSetMAC_REG_DEBUG_PIPE4_skp_acc_counter(unsigned int uskp_acc_counter);
int iSetMAC_REG_DEBUG_PIPE4_mac_ltssm_st(unsigned int umac_ltssm_st);
int iSetMAC_REG_DEBUG_PIPE4_rx_link_speed(unsigned int urx_link_speed);
int iSetMAC_REG_DEBUG_PIPE4_mac_rate(unsigned int umac_rate);
int iSetMAC_REG_DEBUG_RXDLI_1_rxdli_st(unsigned int urxdli_st);
int iSetMAC_REG_DEBUG_RXDLI_1_mac_rx_data_enable(unsigned int umac_rx_data_enable);
int iSetMAC_REG_DEBUG_RXDLI_1_mac_rx_null(unsigned int umac_rx_null);
int iSetMAC_REG_DEBUG_RXDLI_1_mac_rx_err(unsigned int umac_rx_err);
int iSetMAC_REG_DEBUG_RXDLI_1_mac_rx_end(unsigned int umac_rx_end);
int iSetMAC_REG_DEBUG_RXDLI_1_mac_rx_str(unsigned int umac_rx_str);
int iSetMAC_REG_DEBUG_LINK_NUM_1_cur_tx_link_num_1(unsigned int ucur_tx_link_num_1);
int iSetMAC_REG_DEBUG_LANE_NUM_1_cur_tx_lane_num_1(unsigned int ucur_tx_lane_num_1);
int iSetMAC_REG_DEBUG_TXDLI_rxdli_bus_cnt(unsigned int urxdli_bus_cnt);
int iSetMAC_REG_DEBUG_TXDLI_rxdli_have_tlp(unsigned int urxdli_have_tlp);
int iSetMAC_REG_DEBUG_TXDLI_rxdli_have_pkt(unsigned int urxdli_have_pkt);
int iSetMAC_REG_DEBUG_TXDLI_rxdli_data_offset(unsigned int urxdli_data_offset);
int iSetMAC_REG_DEBUG_TXDLI_rxdli_str_offset(unsigned int urxdli_str_offset);
int iSetMAC_REG_DEBUG_TXDLI_block_symbol_count(unsigned int ublock_symbol_count);
int iSetMAC_REG_DEBUG_TXDLI_tx_dli_fsm(unsigned int utx_dli_fsm);
int iSetMAC_REG_LTSSM_TRACER_OUTPUT_1_suceessful_speed_negotiation(unsigned int usuceessful_speed_negotiation);
int iSetMAC_REG_LTSSM_TRACER_OUTPUT_1_changed_speed_recovery(unsigned int uchanged_speed_recovery);
int iSetMAC_REG_LTSSM_TRACER_OUTPUT_1_any_lane_rcv_speed_change(unsigned int uany_lane_rcv_speed_change);
int iSetMAC_REG_LTSSM_TRACER_OUTPUT_1_rxl0s_to_recovery(unsigned int urxl0s_to_recovery);
int iSetMAC_REG_LTSSM_TRACER_OUTPUT_1_any_det_eieos_ts(unsigned int uany_det_eieos_ts);
int iSetMAC_REG_LTSSM_TRACER_OUTPUT_1_directed_speed_change(unsigned int udirected_speed_change);
int iSetMAC_REG_LTSSM_TRACER_OUTPUT_1_all_phy_rxeleidle_or_rx_skp_interval_timeout(unsigned int uall_phy_rxeleidle_or_rx_skp_interval_timeout);
int iSetMAC_REG_LTSSM_TRACER_OUTPUT_1_dl_retrain(unsigned int udl_retrain);
int iSetMAC_REG_LTSSM_TRACER_OUTPUT_1_rcv_eios(unsigned int urcv_eios);
int iSetMAC_REG_LTSSM_TRACER_OUTPUT_1_any_change_pipe_req(unsigned int uany_change_pipe_req);
int iSetMAC_REG_LTSSM_TRACER_OUTPUT_1_rxl0s_st(unsigned int urxl0s_st);
int iSetMAC_REG_LTSSM_TRACER_OUTPUT_1_train_bit_map(unsigned int utrain_bit_map);
int iSetMAC_REG_LTSSM_TRACER_OUTPUT_1_mac_rate(unsigned int umac_rate);
int iSetMAC_REG_LTSSM_TRACER_OUTPUT_1_duration_counter(unsigned int uduration_counter);
int iSetMAC_REG_LTSSM_TRACER_OUTPUT_1_ltssm_st(unsigned int ultssm_st);
int iSetMAC_REG_LTSSM_TRACER_LAST_ADDR_ltssm_tracer_addr_rollback(unsigned int ultssm_tracer_addr_rollback);
int iSetMAC_REG_LTSSM_TRACER_LAST_ADDR_ltssm_tracer_last_waddr(unsigned int ultssm_tracer_last_waddr);
int iSetMAC_REG_SYMBOL_UNLOCL_COUNTER_symbol_unlock_counter(unsigned int usymbol_unlock_counter);
int iSetMAC_REG_MAC_INT_RO_reg_enter_g4_recovery_speed_intr_status_ro(unsigned int ureg_enter_g4_recovery_speed_intr_status_ro);
int iSetMAC_REG_MAC_INT_RO_reg_enter_lpbk_lock_intr_status_ro(unsigned int ureg_enter_lpbk_lock_intr_status_ro);
int iSetMAC_REG_MAC_INT_RO_reg_ltssm_intr_status_ro(unsigned int ureg_ltssm_intr_status_ro);
int iSetMAC_REG_MAC_INT_RO_reg_enter_g3_recovery_speed_intr_status_ro(unsigned int ureg_enter_g3_recovery_speed_intr_status_ro);
int iSetMAC_REG_MAC_INT_RO_reg_enter_g2_recovery_speed_intr_status_ro(unsigned int ureg_enter_g2_recovery_speed_intr_status_ro);
int iSetMAC_REG_MAC_INT_RO_reg_enter_g1_recovery_speed_intr_status_ro(unsigned int ureg_enter_g1_recovery_speed_intr_status_ro);
int iSetMAC_REG_MAC_INT_RO_ltssm_tracer_sram_ecc_2bit_err_intr_status_ro(unsigned int ultssm_tracer_sram_ecc_2bit_err_intr_status_ro);
int iSetMAC_REG_MAC_INT_RO_ltssm_tracer_sram_ecc_1bit_err_intr_status_ro(unsigned int ultssm_tracer_sram_ecc_1bit_err_intr_status_ro);
int iSetMAC_REG_MAC_INT_RO_reg_eco_int_3(unsigned int ureg_eco_int_3);
int iSetMAC_REG_MAC_INT_RO_reg_eco_int_2(unsigned int ureg_eco_int_2);
int iSetMAC_REG_MAC_INT_RO_reg_eco_int_1(unsigned int ureg_eco_int_1);
int iSetMAC_REG_MAC_INT_RO_reg_eco_int_0(unsigned int ureg_eco_int_0);
int iSetMAC_REG_MAC_INT_RO_reg_enter_eq_p3_intr_status_ro(unsigned int ureg_enter_eq_p3_intr_status_ro);
int iSetMAC_REG_MAC_INT_RO_reg_enter_recovery_cfg_intr_status_ro(unsigned int ureg_enter_recovery_cfg_intr_status_ro);
int iSetMAC_REG_MAC_INT_RO_reg_enter_recovery_lock_intr_status_ro(unsigned int ureg_enter_recovery_lock_intr_status_ro);
int iSetMAC_REG_MAC_INT_RO_reg_enter_l2_timeout_intr_status_ro(unsigned int ureg_enter_l2_timeout_intr_status_ro);
int iSetMAC_REG_MAC_INT_RO_reg_enter_l1_timeout_intr_status_ro(unsigned int ureg_enter_l1_timeout_intr_status_ro);
int iSetMAC_REG_MAC_INT_RO_reg_deskew_fifo_overflow_intr_status_ro(unsigned int ureg_deskew_fifo_overflow_intr_status_ro);
int iSetMAC_REG_MAC_INT_RO_reg_loopback_unlock_intr_status_ro(unsigned int ureg_loopback_unlock_intr_status_ro);
int iSetMAC_REG_MAC_INT_RO_reg_symbol_unlock_intr_status_ro(unsigned int ureg_symbol_unlock_intr_status_ro);
int iSetMAC_REG_MAC_INT_RO_reg_deskew_unlock_intr_status_ro(unsigned int ureg_deskew_unlock_intr_status_ro);
int iSetMAC_REG_MAC_INT_RO_reg_phystatus_timeout_intr_status_ro(unsigned int ureg_phystatus_timeout_intr_status_ro);
int iSetMAC_REG_MAC_INT_RO_rxl0s_to_recovery_intr_status_ro(unsigned int urxl0s_to_recovery_intr_status_ro);
int iSetMAC_REG_MAC_INT_RO_reg_hot_reset_intr_status_ro(unsigned int ureg_hot_reset_intr_status_ro);
int iSetMAC_REG_MAC_INT_RO_reg_leave_disable_intr_status_ro(unsigned int ureg_leave_disable_intr_status_ro);
int iSetMAC_REG_MAC_INT_RO_reg_enter_disable_intr_status_ro(unsigned int ureg_enter_disable_intr_status_ro);
int iSetMAC_REG_MAC_INT_RO_reg_leave_l0_intr_status_ro(unsigned int ureg_leave_l0_intr_status_ro);
int iSetMAC_REG_MAC_INT_RO_reg_enter_l0_intr_status_ro(unsigned int ureg_enter_l0_intr_status_ro);
int iSetMAC_REG_MAC_INT_RO_reg_linkdown_intr_status_ro(unsigned int ureg_linkdown_intr_status_ro);
int iSetMAC_REG_MAC_INT_RO_reg_linkup_intr_status_ro(unsigned int ureg_linkup_intr_status_ro);
int iSetMAC_REG_MAC_INT_SET_reg_enter_g4_recovery_speed_intr_set(unsigned int ureg_enter_g4_recovery_speed_intr_set);
int iSetMAC_REG_MAC_INT_SET_reg_enter_lpbk_lock_intr_set(unsigned int ureg_enter_lpbk_lock_intr_set);
int iSetMAC_REG_MAC_INT_SET_reg_ltssm_intr_set(unsigned int ureg_ltssm_intr_set);
int iSetMAC_REG_MAC_INT_SET_reg_enter_g3_recovery_speed_intr_set(unsigned int ureg_enter_g3_recovery_speed_intr_set);
int iSetMAC_REG_MAC_INT_SET_reg_enter_g2_recovery_speed_intr_set(unsigned int ureg_enter_g2_recovery_speed_intr_set);
int iSetMAC_REG_MAC_INT_SET_reg_enter_g1_recovery_speed_intr_set(unsigned int ureg_enter_g1_recovery_speed_intr_set);
int iSetMAC_REG_MAC_INT_SET_ltssm_tracer_sram_ecc_2bit_err_intr_set(unsigned int ultssm_tracer_sram_ecc_2bit_err_intr_set);
int iSetMAC_REG_MAC_INT_SET_ltssm_tracer_sram_ecc_1bit_err_intr_set(unsigned int ultssm_tracer_sram_ecc_1bit_err_intr_set);
int iSetMAC_REG_MAC_INT_SET_eco_int_set_3(unsigned int ueco_int_set_3);
int iSetMAC_REG_MAC_INT_SET_eco_int_set_2(unsigned int ueco_int_set_2);
int iSetMAC_REG_MAC_INT_SET_eco_int_set_1(unsigned int ueco_int_set_1);
int iSetMAC_REG_MAC_INT_SET_eco_int_set_0(unsigned int ueco_int_set_0);
int iSetMAC_REG_MAC_INT_SET_reg_enter_eq_p3_intr_status_set(unsigned int ureg_enter_eq_p3_intr_status_set);
int iSetMAC_REG_MAC_INT_SET_reg_enter_recovery_cfg_intr_status_set(unsigned int ureg_enter_recovery_cfg_intr_status_set);
int iSetMAC_REG_MAC_INT_SET_reg_enter_recovery_lock_intr_status_set(unsigned int ureg_enter_recovery_lock_intr_status_set);
int iSetMAC_REG_MAC_INT_SET_reg_enter_l2_timeout_intr_status_set(unsigned int ureg_enter_l2_timeout_intr_status_set);
int iSetMAC_REG_MAC_INT_SET_reg_enter_l1_timeout_intr_status_set(unsigned int ureg_enter_l1_timeout_intr_status_set);
int iSetMAC_REG_MAC_INT_SET_reg_deskew_fifo_overflow_intr_status_set(unsigned int ureg_deskew_fifo_overflow_intr_status_set);
int iSetMAC_REG_MAC_INT_SET_reg_loopback_unlock_intr_status_set(unsigned int ureg_loopback_unlock_intr_status_set);
int iSetMAC_REG_MAC_INT_SET_reg_symbol_unlock_intr_status_set(unsigned int ureg_symbol_unlock_intr_status_set);
int iSetMAC_REG_MAC_INT_SET_reg_deskew_unlock_intr_status_set(unsigned int ureg_deskew_unlock_intr_status_set);
int iSetMAC_REG_MAC_INT_SET_reg_phystatus_timeout_intr_status_set(unsigned int ureg_phystatus_timeout_intr_status_set);
int iSetMAC_REG_MAC_INT_SET_rxl0s_to_recovery_intr_status_set(unsigned int urxl0s_to_recovery_intr_status_set);
int iSetMAC_REG_MAC_INT_SET_reg_hot_reset_intr_status_set(unsigned int ureg_hot_reset_intr_status_set);
int iSetMAC_REG_MAC_INT_SET_reg_leave_disable_intr_status_set(unsigned int ureg_leave_disable_intr_status_set);
int iSetMAC_REG_MAC_INT_SET_reg_enter_disable_intr_status_set(unsigned int ureg_enter_disable_intr_status_set);
int iSetMAC_REG_MAC_INT_SET_reg_leave_l0_intr_status_set(unsigned int ureg_leave_l0_intr_status_set);
int iSetMAC_REG_MAC_INT_SET_reg_enter_l0_intr_status_set(unsigned int ureg_enter_l0_intr_status_set);
int iSetMAC_REG_MAC_INT_SET_reg_linkdown_intr_status_set(unsigned int ureg_linkdown_intr_status_set);
int iSetMAC_REG_MAC_INT_SET_reg_linkup_intr_status_set(unsigned int ureg_linkup_intr_status_set);
int iSetMAC_REG_ENTER_L1L2_TIMEOUT_VAL_reg_enter_l1l2_timeout_val(unsigned int ureg_enter_l1l2_timeout_val);
int iSetMAC_REG_EQ_FIX_LP_TX_PRESET_reg_comp_lpbk_remote_16g_tx_preset(unsigned int ureg_comp_lpbk_remote_16g_tx_preset);
int iSetMAC_REG_EQ_FIX_LP_TX_PRESET_reg_comp_lpbk_remote_8g_tx_preset(unsigned int ureg_comp_lpbk_remote_8g_tx_preset);
int iSetMAC_REG_EQ_FIX_LP_TX_PRESET_reg_16g_eq_fix_lp_tx_preset(unsigned int ureg_16g_eq_fix_lp_tx_preset);
int iSetMAC_REG_EQ_FIX_LP_TX_PRESET_reg_8g_eq_fix_lp_tx_preset(unsigned int ureg_8g_eq_fix_lp_tx_preset);
int iSetMAC_REG_ADJ_HILINK_MODE_EN_reg_16g_ds_use_rx_preset_en(unsigned int ureg_16g_ds_use_rx_preset_en);
int iSetMAC_REG_ADJ_HILINK_MODE_EN_reg_16g_hilink_mode_en(unsigned int ureg_16g_hilink_mode_en);
int iSetMAC_REG_ADJ_HILINK_MODE_EN_gen4_eq_phase23_ffe_ctle_adj_en(unsigned int ugen4_eq_phase23_ffe_ctle_adj_en);
int iSetMAC_REG_ADJ_HILINK_MODE_EN_gen3_eq_phase23_ffe_ctle_adj_en(unsigned int ugen3_eq_phase23_ffe_ctle_adj_en);
int iSetMAC_REG_ADJ_HILINK_MODE_EN_gen4_eq_phase01_ctle_apt_en(unsigned int ugen4_eq_phase01_ctle_apt_en);
int iSetMAC_REG_ADJ_HILINK_MODE_EN_gen3_eq_phase01_ctle_apt_en(unsigned int ugen3_eq_phase01_ctle_apt_en);
int iSetMAC_REG_ADJ_HILINK_MODE_EN_gen4_eq_phase23_ctle_apt_en(unsigned int ugen4_eq_phase23_ctle_apt_en);
int iSetMAC_REG_ADJ_HILINK_MODE_EN_gen4_eq_rcv_lock_af_phase13_ctle_apt_en(unsigned int ugen4_eq_rcv_lock_af_phase13_ctle_apt_en);
int iSetMAC_REG_ADJ_HILINK_MODE_EN_reg_switch_eq_mode_mask(unsigned int ureg_switch_eq_mode_mask);
int iSetMAC_REG_ADJ_HILINK_MODE_EN_rcv_lock_hold_rate(unsigned int urcv_lock_hold_rate);
int iSetMAC_REG_ADJ_HILINK_MODE_EN_gen3_eq_phase23_ctle_apt_en(unsigned int ugen3_eq_phase23_ctle_apt_en);
int iSetMAC_REG_ADJ_HILINK_MODE_EN_rcv_speed_pull_up_rx_preset_en(unsigned int urcv_speed_pull_up_rx_preset_en);
int iSetMAC_REG_ADJ_HILINK_MODE_EN_gen3_eq_rcv_lock_af_phase13_ctle_apt_en(unsigned int ugen3_eq_rcv_lock_af_phase13_ctle_apt_en);
int iSetMAC_REG_ADJ_HILINK_MODE_EN_reg_8g_hilink_mode_en(unsigned int ureg_8g_hilink_mode_en);
int iSetMAC_REG_LP_GEN3_TX_PRESET_P1_1_lp_gen3_tx_preset_p1_1(unsigned int ulp_gen3_tx_preset_p1_1);
int iSetMAC_REG_EQ_OPT_TX_PRESET_1_opt_gen3_preset_1(unsigned int uopt_gen3_preset_1);
int iSetMAC_REG_LOOPBACK_PRESET_TIMEOUT_VAL_ADDR_reg_loopback_preset_timeout_val(unsigned int ureg_loopback_preset_timeout_val);
int iSetMAC_REG_COMP_OPTION_reg_comp_option_en(unsigned int ureg_comp_option_en);
int iSetMAC_REG_PHY_RXDATA_TS_phy_rxdata_ts(unsigned int uphy_rxdata_ts);
int iSetMAC_REG_ECO_RSV0_mac_eco_rsv0(unsigned int umac_eco_rsv0);
int iSetMAC_REG_ECO_RSV1_mac_eco_rsv1(unsigned int umac_eco_rsv1);
int iSetMAC_REG_ECO_RSV1_reg_pm_irs_empty_mask(unsigned int ureg_pm_irs_empty_mask);
int iSetMAC_REGEQ_TRACE_coeff_search_tracer_lane_num(unsigned int ucoeff_search_tracer_lane_num);
int iSetMAC_REGEQ_TRACE_coeff_search_tracer_addr_rollback(unsigned int ucoeff_search_tracer_addr_rollback);
int iSetMAC_REGEQ_TRACE_coeff_search_tracer_last_waddr(unsigned int ucoeff_search_tracer_last_waddr);
int iSetMAC_REGEQ_TRACE_coeff_search_tracer_raddr(unsigned int ucoeff_search_tracer_raddr);
int iSetMAC_REGEQ_TRACE_coeff_search_tracer_mode(unsigned int ucoeff_search_tracer_mode);
int iSetMAC_REGEQ_TRACE_coeff_search_tracer_cap_mode(unsigned int ucoeff_search_tracer_cap_mode);
int iSetMAC_REGEQ_TRACE_coeff_search_tracer_recap(unsigned int ucoeff_search_tracer_recap);
int iSetMAC_REG_EQ_TIMEOUT_SET_cfg_coeff_req_timeout_val(unsigned int ucfg_coeff_req_timeout_val);
int iSetMAC_REG_EQ_TIMEOUT_SET_cfg_coeff_search_22ms_timeout(unsigned int ucfg_coeff_search_22ms_timeout);
int iSetMAC_REG_EQ_INIT_COEFF_CFG_preset_coeff_maping_table_index(unsigned int upreset_coeff_maping_table_index);
int iSetMAC_REG_EQ_INIT_COEFF_CFG_cfg_init_coeff(unsigned int ucfg_init_coeff);
int iSetMAC_REG_WAIT_LINK_NUM_TIMER_wait_ts1_num(unsigned int uwait_ts1_num);
int iSetMAC_REG_WAIT_LINK_NUM_TIMER_wait_link_num_timer_dp(unsigned int uwait_link_num_timer_dp);
int iSetMAC_REG_LANE_COEFF_1_reg_1_lane_c1(unsigned int ureg_1_lane_c1);
int iSetMAC_REG_LANE_COEFF_1_reg_1_lane_c0(unsigned int ureg_1_lane_c0);
int iSetMAC_REG_LANE_COEFF_1_reg_1_lane_cm1(unsigned int ureg_1_lane_cm1);
int iSetMAC_REG_PRESET0_reg_preset0_c1(unsigned int ureg_preset0_c1);
int iSetMAC_REG_PRESET0_reg_preset0_c0(unsigned int ureg_preset0_c0);
int iSetMAC_REG_PRESET0_reg_preset0_cm1(unsigned int ureg_preset0_cm1);
int iSetMAC_REG_PRESET1_reg_preset1_c1(unsigned int ureg_preset1_c1);
int iSetMAC_REG_PRESET1_reg_preset1_c0(unsigned int ureg_preset1_c0);
int iSetMAC_REG_PRESET1_reg_preset1_cm1(unsigned int ureg_preset1_cm1);
int iSetMAC_REG_PRESET2_reg_preset2_c1(unsigned int ureg_preset2_c1);
int iSetMAC_REG_PRESET2_reg_preset2_c0(unsigned int ureg_preset2_c0);
int iSetMAC_REG_PRESET2_reg_preset2_cm1(unsigned int ureg_preset2_cm1);
int iSetMAC_REG_PRESET3_reg_preset3_c1(unsigned int ureg_preset3_c1);
int iSetMAC_REG_PRESET3_reg_preset3_c0(unsigned int ureg_preset3_c0);
int iSetMAC_REG_PRESET3_reg_preset3_cm1(unsigned int ureg_preset3_cm1);
int iSetMAC_REG_PRESET4_reg_preset4_c1(unsigned int ureg_preset4_c1);
int iSetMAC_REG_PRESET4_reg_preset4_c0(unsigned int ureg_preset4_c0);
int iSetMAC_REG_PRESET4_reg_preset4_cm1(unsigned int ureg_preset4_cm1);
int iSetMAC_REG_PRESET5_reg_preset5_c1(unsigned int ureg_preset5_c1);
int iSetMAC_REG_PRESET5_reg_preset5_c0(unsigned int ureg_preset5_c0);
int iSetMAC_REG_PRESET5_reg_preset5_cm1(unsigned int ureg_preset5_cm1);
int iSetMAC_REG_PRESET6_reg_preset6_c1(unsigned int ureg_preset6_c1);
int iSetMAC_REG_PRESET6_reg_preset6_c0(unsigned int ureg_preset6_c0);
int iSetMAC_REG_PRESET6_reg_preset6_cm1(unsigned int ureg_preset6_cm1);
int iSetMAC_REG_PRESET7_reg_preset7_c1(unsigned int ureg_preset7_c1);
int iSetMAC_REG_PRESET7_reg_preset7_c0(unsigned int ureg_preset7_c0);
int iSetMAC_REG_PRESET7_reg_preset7_cm1(unsigned int ureg_preset7_cm1);
int iSetMAC_REG_PRESET8_reg_preset8_c1(unsigned int ureg_preset8_c1);
int iSetMAC_REG_PRESET8_reg_preset8_c0(unsigned int ureg_preset8_c0);
int iSetMAC_REG_PRESET8_reg_preset8_cm1(unsigned int ureg_preset8_cm1);
int iSetMAC_REG_PRESET9_reg_preset9_c1(unsigned int ureg_preset9_c1);
int iSetMAC_REG_PRESET9_reg_preset9_c0(unsigned int ureg_preset9_c0);
int iSetMAC_REG_PRESET9_reg_preset9_cm1(unsigned int ureg_preset9_cm1);
int iSetMAC_REG_PRESET10_reg_preset10_c1(unsigned int ureg_preset10_c1);
int iSetMAC_REG_PRESET10_reg_preset10_c0(unsigned int ureg_preset10_c0);
int iSetMAC_REG_PRESET10_reg_preset10_cm1(unsigned int ureg_preset10_cm1);
int iSetMAC_REG_PRESET11_reg_preset11_c1(unsigned int ureg_preset11_c1);
int iSetMAC_REG_PRESET11_reg_preset11_c0(unsigned int ureg_preset11_c0);
int iSetMAC_REG_PRESET11_reg_preset11_cm1(unsigned int ureg_preset11_cm1);
int iSetMAC_REG_PRESET12_reg_preset12_c1(unsigned int ureg_preset12_c1);
int iSetMAC_REG_PRESET12_reg_preset12_c0(unsigned int ureg_preset12_c0);
int iSetMAC_REG_PRESET12_reg_preset12_cm1(unsigned int ureg_preset12_cm1);
int iSetMAC_REG_PRESET13_reg_preset13_c1(unsigned int ureg_preset13_c1);
int iSetMAC_REG_PRESET13_reg_preset13_c0(unsigned int ureg_preset13_c0);
int iSetMAC_REG_PRESET13_reg_preset13_cm1(unsigned int ureg_preset13_cm1);
int iSetMAC_REG_PRESET14_reg_preset14_c1(unsigned int ureg_preset14_c1);
int iSetMAC_REG_PRESET14_reg_preset14_c0(unsigned int ureg_preset14_c0);
int iSetMAC_REG_PRESET14_reg_preset14_cm1(unsigned int ureg_preset14_cm1);
int iSetMAC_REG_PRESET15_reg_preset15_c1(unsigned int ureg_preset15_c1);
int iSetMAC_REG_PRESET15_reg_preset15_c0(unsigned int ureg_preset15_c0);
int iSetMAC_REG_PRESET15_reg_preset15_cm1(unsigned int ureg_preset15_cm1);
int iSetMAC_REG_DEBUG_PIPE5_mac_ltssm_st(unsigned int umac_ltssm_st);
int iSetMAC_REG_DEBUG_PIPE5_mac_txeleidle(unsigned int umac_txeleidle);
int iSetMAC_REG_DEBUG_PIPE6_mac_ltssm_st(unsigned int umac_ltssm_st);
int iSetMAC_REG_DEBUG_PIPE6_mac_rxpolarity(unsigned int umac_rxpolarity);
int iSetMAC_REG_DEBUG_PIPE7_mac_ltssm_st(unsigned int umac_ltssm_st);
int iSetMAC_REG_DEBUG_PIPE7_mac_powerdown_1(unsigned int umac_powerdown_1);
int iSetMAC_REG_DEBUG_PIPE8_mac_ltssm_st(unsigned int umac_ltssm_st);
int iSetMAC_REG_DEBUG_PIPE8_phy_txdetrx(unsigned int uphy_txdetrx);
int iSetMAC_REG_DEBUG_PIPE9_mac_ltssm_st(unsigned int umac_ltssm_st);
int iSetMAC_REG_DEBUG_PIPE9_phy_rxeleidle(unsigned int uphy_rxeleidle);
int iSetMAC_REG_DEBUG_PIPE10_mac_ltssm_st(unsigned int umac_ltssm_st);
int iSetMAC_REG_DEBUG_PIPE10_phy_rxdata_valid(unsigned int uphy_rxdata_valid);
int iSetMAC_REG_DEBUG_PIPE11_mac_ltssm_st(unsigned int umac_ltssm_st);
int iSetMAC_REG_DEBUG_PIPE11_phy_rxvalid(unsigned int uphy_rxvalid);
int iSetMAC_REG_DEBUG_RXDLI_2_mac_rx_seq(unsigned int umac_rx_seq);
int iSetMAC_REG_DEBUG_LINK_NUM_2_cur_tx_link_num_2(unsigned int ucur_tx_link_num_2);
int iSetMAC_REG_DEBUG_LINK_NUM_3_cur_tx_link_num_3(unsigned int ucur_tx_link_num_3);
int iSetMAC_REG_DEBUG_LINK_NUM_4_cur_tx_link_num_4(unsigned int ucur_tx_link_num_4);
int iSetMAC_REG_DEBUG_LANE_NUM_2_cur_tx_lane_num_2(unsigned int ucur_tx_lane_num_2);
int iSetMAC_REG_DEBUG_LANE_NUM_3_cur_tx_lane_num_3(unsigned int ucur_tx_lane_num_3);
int iSetMAC_REG_DEBUG_LANE_NUM_4_cur_tx_lane_num_4(unsigned int ucur_tx_lane_num_4);
int iSetMAC_REG_LP_GEN3_TX_PRESET_P1_2_lp_gen3_tx_preset_p1_2(unsigned int ulp_gen3_tx_preset_p1_2);
int iSetMAC_REG_GEN3_EQ_OPT_TX_PRESET_2_opt_gen3_preset_2(unsigned int uopt_gen3_preset_2);
int iSetMAC_REG_LANE_COEFF_2_reg_2_lane_c1(unsigned int ureg_2_lane_c1);
int iSetMAC_REG_LANE_COEFF_2_reg_2_lane_c0(unsigned int ureg_2_lane_c0);
int iSetMAC_REG_LANE_COEFF_2_reg_2_lane_cm1(unsigned int ureg_2_lane_cm1);
int iSetMAC_REG_LTSSM_TRACER_OUTPUT_2_txdetrx(unsigned int utxdetrx);
int iSetMAC_REG_LTSSM_TRACER_OUTPUT_2_train_bit_map(unsigned int utrain_bit_map);
int iSetMAC_REG_LTSSM_TRACER_OUTPUT_OK_ltssm_tracer_data_ok(unsigned int ultssm_tracer_data_ok);
int iSetMAC_REG_LTSSM_TRACER_SRAM_ECC_INSERT_ltssm_tracer_sram_ecc_insert(unsigned int ultssm_tracer_sram_ecc_insert);
int iSetMAC_REG_LTSSM_TRACER_ECC_ERR_ADDR_ecc_2bit_err_addr(unsigned int uecc_2bit_err_addr);
int iSetMAC_REG_LTSSM_TRACER_ECC_ERR_ADDR_ecc_1bit_err_addr(unsigned int uecc_1bit_err_addr);
int iSetMAC_REG_COEFF_SEARCH_TRACER_OUTPUT_req_pre_cur_coeff(unsigned int ureq_pre_cur_coeff);
int iSetMAC_REG_COEFF_SEARCH_TRACER_OUTPUT_req_cur_coeff(unsigned int ureq_cur_coeff);
int iSetMAC_REG_COEFF_SEARCH_TRACER_OUTPUT_fig_merit_feedback(unsigned int ufig_merit_feedback);
int iSetMAC_REG_COEFF_SEARCH_TRACER_OUTPUT_fsm_curr_search_state(unsigned int ufsm_curr_search_state);
int iSetMAC_REG_COEFF_SEARCH_TRACER_OUTPUT_total_search_num(unsigned int utotal_search_num);
int iSetMAC_REG_REMOTE_FS_LF_remote_fs(unsigned int uremote_fs);
int iSetMAC_REG_REMOTE_FS_LF_remote_lf(unsigned int uremote_lf);
int iSetMAC_LOOP_LINK_DATA_ERR_COUNT_loop_back_link_data_err_cnt(unsigned int uloop_back_link_data_err_cnt);
int iSetMAC_PCS_RX_ERR_CNT_pcs_rx_err_cnt(unsigned int upcs_rx_err_cnt);
int iSetMAC_UP_MAX_AUTO_REDO_NUM_req_rx_req_eq_ts_count(unsigned int ureq_rx_req_eq_ts_count);
int iSetMAC_UP_MAX_AUTO_REDO_NUM_req_dp_redo_eq_gnt_mask(unsigned int ureq_dp_redo_eq_gnt_mask);
int iSetMAC_UP_MAX_AUTO_REDO_NUM_permit_up_redo_eq(unsigned int upermit_up_redo_eq);
int iSetMAC_WAIT_LANE_NUM_TIMER_cfg_lnacc_wait_lane_ts1_num(unsigned int ucfg_lnacc_wait_lane_ts1_num);
int iSetMAC_WAIT_LANE_NUM_TIMER_cfg_wait_lane_ts1_num(unsigned int ucfg_wait_lane_ts1_num);
int iSetMAC_WAIT_LANE_NUM_TIMER_cfg_wait_lane_num_timer_dp(unsigned int ucfg_wait_lane_num_timer_dp);
int iSetMAC_LANE_NUM_WAIT_TIMER_wait_link_num_timer_up(unsigned int uwait_link_num_timer_up);
int iSetMAC_LANE_NUM_WAIT_TIMER_reg_lane_num_wait_timer(unsigned int ureg_lane_num_wait_timer);
int iSetMAC_LANE_NUM_ACC_TIMER_cfg_wait_lane_num_timer_up(unsigned int ucfg_wait_lane_num_timer_up);
int iSetMAC_LANE_NUM_ACC_TIMER_reg_lane_num_acc_timer(unsigned int ureg_lane_num_acc_timer);
int iSetMAC_LNW_TO_LNA_1MS_TIMER_cfg_lnw_to_lna_1ms_timer(unsigned int ucfg_lnw_to_lna_1ms_timer);
int iSetMAC_EQ_LTSMM_HOLD_TIMER_cfg_phase0_hold_timer(unsigned int ucfg_phase0_hold_timer);
int iSetMAC_EQ_LTSMM_HOLD_TIMER_cfg_rcv_lock_hold_timer(unsigned int ucfg_rcv_lock_hold_timer);
int iSetMAC_EQ_LTSMM_HOLD_TIMER_cfg_phase23_hold_timer(unsigned int ucfg_phase23_hold_timer);
int iSetMAC_LTSSM_CRTL_INFER_ELECIDLE_reg_mask_datapath_rxelecidle(unsigned int ureg_mask_datapath_rxelecidle);
int iSetMAC_LTSSM_CRTL_INFER_ELECIDLE_reg_use_any_lane_infer_eleidle(unsigned int ureg_use_any_lane_infer_eleidle);
int iSetMAC_LTSSM_CRTL_INFER_ELECIDLE_set_rx_elecidle_infer(unsigned int uset_rx_elecidle_infer);
int iSetMAC_LTSSM_CRTL_INFER_ELECIDLE_rx_elecidle_infer_interval_timout_mask(unsigned int urx_elecidle_infer_interval_timout_mask);
int iSetMAC_LTSSM_TRACER_CFG0_sel_trace_rx_data_mode(unsigned int usel_trace_rx_data_mode);
int iSetMAC_LTSSM_TRACER_CFG0_ltssm_trace_lane_num(unsigned int ultssm_trace_lane_num);
int iSetMAC_LTSSM_TRACER_CFG0_ltssm_trace_timer_clk_sel(unsigned int ultssm_trace_timer_clk_sel);
int iSetMAC_LTSSM_TRACER_CFG0_ltssm_trace_signal_mask(unsigned int ultssm_trace_signal_mask);
int iSetMAC_LTSSM_TRACER_CFG1_clr_ltssm_trace_timer(unsigned int uclr_ltssm_trace_timer);
int iSetMAC_LTSSM_TRACER_CFG1_ltssm_trace_state(unsigned int ultssm_trace_state);
int iSetMAC_LTSSM_TRACER_CFG1_ltssm_trace_trigger_timer(unsigned int ultssm_trace_trigger_timer);
int iSetMAC_CMP_LOOP_SENT_EQTS1_reg_mac_tx_sent_eq_ts1(unsigned int ureg_mac_tx_sent_eq_ts1);
int iSetMAC_ENTER_LPBK_DISABLE_disable_scramber_disable(unsigned int udisable_scramber_disable);
int iSetMAC_ENTER_LPBK_DISABLE_reg_new_gen4_eieos_en(unsigned int ureg_new_gen4_eieos_en);
int iSetMAC_ENTER_LPBK_DISABLE_reg_disable_ctrl_skp(unsigned int ureg_disable_ctrl_skp);
int iSetMAC_ENTER_LPBK_DISABLE_gen3_low_latency_mode(unsigned int ugen3_low_latency_mode);
int iSetMAC_ENTER_LPBK_DISABLE_disable_enter_compliance(unsigned int udisable_enter_compliance);
int iSetMAC_ENTER_LPBK_DISABLE_auto_speed_change_en(unsigned int uauto_speed_change_en);
int iSetMAC_ENTER_LPBK_DISABLE_first_auto_speed_change_en(unsigned int ufirst_auto_speed_change_en);
int iSetMAC_ENTER_LPBK_DISABLE_auto_speed_disable_mask(unsigned int uauto_speed_disable_mask);
int iSetMAC_ENTER_LPBK_DISABLE_disable_enter_hotreset(unsigned int udisable_enter_hotreset);
int iSetMAC_ENTER_LPBK_DISABLE_disable_enter_disable(unsigned int udisable_enter_disable);
int iSetMAC_ENTER_LPBK_DISABLE_disable_enter_loopback(unsigned int udisable_enter_loopback);
int iSetMAC_PRESET_TABLE0_mac_preset_table0(unsigned int umac_preset_table0);
int iSetMAC_PRESET_TABLE1_reg_preset_num(unsigned int ureg_preset_num);
int iSetMAC_PRESET_TABLE1_mac_preset_table1(unsigned int umac_preset_table1);
int iSetMAC_REG_LTSSM_TRACERADDR_reg_ltssm_tracer_raddr(unsigned int ureg_ltssm_tracer_raddr);
int iSetMAC_CFG_COMPLETE_TIMER_cfg_clp_to_idle_tm_enable(unsigned int ucfg_clp_to_idle_tm_enable);
int iSetMAC_CFG_COMPLETE_TIMER_reg_clp_to_idle_timer(unsigned int ureg_clp_to_idle_timer);
int iSetMAC_CFG_COMP_ERRATA_DISABLE_reg_comp_errata_disable(unsigned int ureg_comp_errata_disable);
int iSetMAC_RX_ERR_CHECK_EN_lane_rx_err_check_en(unsigned int ulane_rx_err_check_en);
int iSetMAC_TRACE_2BIT_ECC_CNT_ecc_2bit_er_cnt(unsigned int uecc_2bit_er_cnt);
int iSetMAC_TRACE_1BIT_ECC_CNT_ecc_1bit_er_cnt(unsigned int uecc_1bit_er_cnt);
int iSetMAC_CFG_RCV_HOLD_EN_reg_rcv_idle_hold_en(unsigned int ureg_rcv_idle_hold_en);
int iSetMAC_CFG_RCV_HOLD_EN_reg_rcv_cfg_hold_en(unsigned int ureg_rcv_cfg_hold_en);
int iSetMAC_CFG_RCV_HOLD_EN_reg_rcv_lock_hold_en(unsigned int ureg_rcv_lock_hold_en);
int iSetMAC_CFG_RCV_LOCK_HOLD_TIME_reg_rcv_lock_hold_time(unsigned int ureg_rcv_lock_hold_time);
int iSetMAC_CFG_RCV_CFG_HOLD_TIME_reg_extended_ts_number(unsigned int ureg_extended_ts_number);
int iSetMAC_CFG_RCV_CFG_HOLD_TIME_reg_rcv_cfg_hold_time(unsigned int ureg_rcv_cfg_hold_time);
int iSetMAC_CFG_RCV_IDLE_HOLD_TIME_reg_detect_wait_time(unsigned int ureg_detect_wait_time);
int iSetMAC_CFG_RCV_IDLE_HOLD_TIME_reg_rcv_idle_hold_time(unsigned int ureg_rcv_idle_hold_time);
int iSetMAC_LTSSM_INT_STATUS_reg_ltssm_int_match_state(unsigned int ureg_ltssm_int_match_state);
int iSetMAC_DESKEW_SYMBOL_UNLOCK_RCV_MASK_reg_deskew_numlock_err_rcv_mask(unsigned int ureg_deskew_numlock_err_rcv_mask);
int iSetMAC_DESKEW_SYMBOL_UNLOCK_RCV_MASK_reg_symbol_numlock_err_rcv_mask(unsigned int ureg_symbol_numlock_err_rcv_mask);
int iSetMAC_REG_GEN4_EQ_OPT_TX_PRESET_1_opt_gen4_preset_1(unsigned int uopt_gen4_preset_1);
int iSetMAC_REG_GEN4_EQ_OPT_TX_PRESET_2_opt_gen4_preset_2(unsigned int uopt_gen4_preset_2);
int iSetMAC_REG_LP_GEN4_TX_PRESET_P1_1_lp_gen4_tx_preset_p1_1(unsigned int ulp_gen4_tx_preset_p1_1);
int iSetMAC_REG_LP_GEN4_TX_PRESET_P1_2_lp_gen4_tx_preset_p1_2(unsigned int ulp_gen4_tx_preset_p1_2);
int iSetMAC_LPBK_DATA_reg_lpbk_data(unsigned int ureg_lpbk_data);
int iSetMAC_RX_MARGIN_SELF_CTRL_reg_dfe_cfg_value(unsigned int ureg_dfe_cfg_value);
int iSetMAC_RX_MARGIN_SELF_CTRL_reg_dfe_disable_cfg_en(unsigned int ureg_dfe_disable_cfg_en);
int iSetMAC_RX_MARGIN_CFG_reg_margin_global_disable(unsigned int ureg_margin_global_disable);
int iSetMAC_RX_MARGIN_CFG_reg_margin_vender_define_cmd_payload(unsigned int ureg_margin_vender_define_cmd_payload);
int iSetGEN4_RX_MARGIN_CPA0_max_voltage_offset(unsigned int umax_voltage_offset);
int iSetGEN4_RX_MARGIN_CPA0_num_voltage_steps(unsigned int unum_voltage_steps);
int iSetGEN4_RX_MARGIN_CPA0_ind_up_down_voltage_support(unsigned int uind_up_down_voltage_support);
int iSetGEN4_RX_MARGIN_CPA0_max_timing_offset(unsigned int umax_timing_offset);
int iSetGEN4_RX_MARGIN_CPA0_voltage_support(unsigned int uvoltage_support);
int iSetGEN4_RX_MARGIN_CPA0_indleft_right_timing_support(unsigned int uindleft_right_timing_support);
int iSetGEN4_RX_MARGIN_CPA0_num_timing_steps(unsigned int unum_timing_steps);
int iSetGEN4_RX_MARGIN_CPA1_sample_rate_voltage(unsigned int usample_rate_voltage);
int iSetGEN4_RX_MARGIN_CPA1_sample_reporting_method(unsigned int usample_reporting_method);
int iSetGEN4_RX_MARGIN_CPA1_ind_error_sample(unsigned int uind_error_sample);
int iSetGEN4_RX_MARGIN_CPA1_sample_rate_timing(unsigned int usample_rate_timing);
int iSetGEN4_RX_MARGIN_CPA1_max_lane_support(unsigned int umax_lane_support);
int iSetGEN4_RX_MARGIN_RSV_rx_margin_rsv(unsigned int urx_margin_rsv);
int iSetMAC_REG_GEN3_EQ_FIX_TX_PRESET_1_reg_fix_8g_tx_preset_value1(unsigned int ureg_fix_8g_tx_preset_value1);
int iSetMAC_REG_GEN3_EQ_FIX_TX_PRESET_2_reg_fix_8g_tx_preset_value2(unsigned int ureg_fix_8g_tx_preset_value2);
int iSetMAC_REG_GEN4_EQ_FIX_TX_PRESET_1_reg_fix_16g_tx_preset_value1(unsigned int ureg_fix_16g_tx_preset_value1);
int iSetMAC_REG_GEN4_EQ_FIX_TX_PRESET_2_reg_fix_16g_tx_preset_value2(unsigned int ureg_fix_16g_tx_preset_value2);
int iSetMAC_REG_PHASE01_COARSETUNE_START_TM_VALUE_resvered(unsigned int uresvered);
int iSetMAC_REG_PHASE01_COARSETUNE_START_TM_VALUE_reg_up_16g_phase1_hold_en(unsigned int ureg_up_16g_phase1_hold_en);
int iSetMAC_REG_PHASE01_COARSETUNE_START_TM_VALUE_reg_up_8g_phase1_hold_en(unsigned int ureg_up_8g_phase1_hold_en);
int iSetMAC_REG_PHASE01_COARSETUNE_START_TM_VALUE_reg_16g_phase01_timeout_skip_en(unsigned int ureg_16g_phase01_timeout_skip_en);
int iSetMAC_REG_PHASE01_COARSETUNE_START_TM_VALUE_reg_8g_phase01_timeout_skip_en(unsigned int ureg_8g_phase01_timeout_skip_en);
int iSetMAC_REG_PHASE01_COARSETUNE_START_TM_VALUE_reg_16g_ignore_ctle_done(unsigned int ureg_16g_ignore_ctle_done);
int iSetMAC_REG_PHASE01_COARSETUNE_START_TM_VALUE_reg_8g_ignore_ctle_done(unsigned int ureg_8g_ignore_ctle_done);
int iSetMAC_REG_PHASE01_COARSETUNE_START_TM_VALUE_reg_coarsetune_start_use_rxvalid_en(unsigned int ureg_coarsetune_start_use_rxvalid_en);
int iSetMAC_REG_PHASE01_COARSETUNE_START_TM_VALUE_reg_coarsetune_start_use_rxidle_en(unsigned int ureg_coarsetune_start_use_rxidle_en);
int iSetMAC_REG_PHASE01_COARSETUNE_START_TM_VALUE_reg_phase01_coarsetune_start_tm(unsigned int ureg_phase01_coarsetune_start_tm);
int iSetMAC_LTSSM_TIMEOUT_ENABLE_resvered(unsigned int uresvered);
int iSetMAC_LTSSM_TIMEOUT_ENABLE_reg_ltssm_timeout_en(unsigned int ureg_ltssm_timeout_en);
int iSetMAC_LOOPBACK_EC_VALUE_loopback_ec_value(unsigned int uloopback_ec_value);
int iSetMAC_LANE_REVERSE_CFG_resver(unsigned int uresver);
int iSetMAC_LANE_REVERSE_CFG_lane0_number(unsigned int ulane0_number);
int iSetMAC_LANE_REVERSE_CFG_resvered(unsigned int uresvered);
int iSetMAC_LANE_REVERSE_CFG_reg_unused_lane_turn_off_en(unsigned int ureg_unused_lane_turn_off_en);
int iSetMAC_LANE_REVERSE_CFG_reg_compliance_mode(unsigned int ureg_compliance_mode);
int iSetMAC_LANE_REVERSE_CFG_reg_lane_reverse_mux_cfg_en(unsigned int ureg_lane_reverse_mux_cfg_en);
int iSetMAC_LANE_REVERSE_CFG_reg_lane_reverse_mux_value(unsigned int ureg_lane_reverse_mux_value);
int iSetMAC_PIPE_SRIS_EN_resvered(unsigned int uresvered);
int iSetMAC_PIPE_SRIS_EN_reg_mac2phy_sris_en(unsigned int ureg_mac2phy_sris_en);
int iSetMAC_PIPE_EBUF_MODE_resvered(unsigned int uresvered);
int iSetMAC_PIPE_EBUF_MODE_reg_mac2phy_ebuf_mode(unsigned int ureg_mac2phy_ebuf_mode);
int iSetMAC_PIPE_SRIS_EN0_reg_ebuff_depth03(unsigned int ureg_ebuff_depth03);
int iSetMAC_PIPE_SRIS_EN1_reg_ebuff_depth47(unsigned int ureg_ebuff_depth47);
int iSetMAC_PIPE_SRIS_EN2_reg_ebuff_depth811(unsigned int ureg_ebuff_depth811);
int iSetMAC_PIPE_SRIS_EN3_reg_ebuff_depth1216(unsigned int ureg_ebuff_depth1216);
int iSetMAC_FRAMING_ERR_CNT_resvered(unsigned int uresvered);
int iSetMAC_FRAMING_ERR_CNT_reg_framing_err_count(unsigned int ureg_framing_err_count);
int iSetMAC_FRAMING_ERR_CTRL_resvered(unsigned int uresvered);
int iSetMAC_FRAMING_ERR_CTRL_reg_framing_mask(unsigned int ureg_framing_mask);
int iSetMAC_FRAMING_ERR_CTRL_reg_pcs_decode_err_retrain_en(unsigned int ureg_pcs_decode_err_retrain_en);
int iSetMAC_FRAMING_ERR_CTRL_reg_framing_err_rpt_en(unsigned int ureg_framing_err_rpt_en);
int iSetMAC_FRAMING_ERR_CTRL_reg_framing_err_retrain_en(unsigned int ureg_framing_err_retrain_en);
int iSetMAC_LINKDOWN_REQ_MASK_resvered(unsigned int uresvered);
int iSetMAC_LINKDOWN_REQ_MASK_reg_mac_linkdown_req_mask(unsigned int ureg_mac_linkdown_req_mask);
int iSetMAC_INT_TYPE_SEL_resvered(unsigned int uresvered);
int iSetMAC_INT_TYPE_SEL_reg_mac_int_type_sel(unsigned int ureg_mac_int_type_sel);
int iSetMAC_REQ_COEFF_INFO_resvered(unsigned int uresvered);
int iSetMAC_REQ_COEFF_INFO_tx_preset(unsigned int utx_preset);
int iSetMAC_REQ_COEFF_INFO_req_pre_cur_coeff(unsigned int ureq_pre_cur_coeff);
int iSetMAC_REQ_COEFF_INFO_req_cur_coeff(unsigned int ureq_cur_coeff);
int iSetMAC_REQ_COEFF_INFO_fig_merit_feedback(unsigned int ufig_merit_feedback);
int iSetMAC_RX_COEFF_INFO_resvered(unsigned int uresvered);
int iSetMAC_RX_COEFF_INFO_rx_xmt_preset(unsigned int urx_xmt_preset);
int iSetMAC_RX_COEFF_INFO_rx_pre_cur_coeff(unsigned int urx_pre_cur_coeff);
int iSetMAC_RX_COEFF_INFO_rx_cur_coeff(unsigned int urx_cur_coeff);
int iSetMAC_RX_COEFF_INFO_rx_use_preset(unsigned int urx_use_preset);
int iSetMAC_RX_COEFF_INFO_rx_post_cur_coeff(unsigned int urx_post_cur_coeff);
int iSetMAC_LEAVE_L0_INFO_resvered(unsigned int uresvered);
int iSetMAC_LEAVE_L0_INFO_rcv_eios(unsigned int urcv_eios);
int iSetMAC_LEAVE_L0_INFO_enter_l1l2_timeout(unsigned int uenter_l1l2_timeout);
int iSetMAC_LEAVE_L0_INFO_enter_l0s_req(unsigned int uenter_l0s_req);
int iSetMAC_LEAVE_L0_INFO_enter_l1_req(unsigned int uenter_l1_req);
int iSetMAC_LEAVE_L0_INFO_enter_l2_req(unsigned int uenter_l2_req);
int iSetMAC_LEAVE_L0_INFO_dl_req_link_down(unsigned int udl_req_link_down);
int iSetMAC_LEAVE_L0_INFO_tl_ap_req_link_down(unsigned int utl_ap_req_link_down);
int iSetMAC_LEAVE_L0_INFO_direct_speed_change(unsigned int udirect_speed_change);
int iSetMAC_LEAVE_L0_INFO_det_ts_train(unsigned int udet_ts_train);
int iSetMAC_LEAVE_L0_INFO_det_eieos_128b130b(unsigned int udet_eieos_128b130b);
int iSetMAC_LEAVE_L0_INFO_reg_retrain_req(unsigned int ureg_retrain_req);
int iSetMAC_LEAVE_L0_INFO_cfg_retrain_req(unsigned int ucfg_retrain_req);
int iSetMAC_LEAVE_L0_INFO_hot_reset(unsigned int uhot_reset);
int iSetMAC_LEAVE_L0_INFO_skp_infter_idle_timeout(unsigned int uskp_infter_idle_timeout);
int iSetMAC_LEAVE_L0_INFO_dl_retran(unsigned int udl_retran);
int iSetMAC_LEAVE_L0_INFO_framing_err_retrain(unsigned int uframing_err_retrain);
int iSetMAC_LEAVE_L0_INFO_enter_loop_back(unsigned int uenter_loop_back);
int iSetMAC_LEAVE_L0_INFO_cfg_link_disable(unsigned int ucfg_link_disable);
int iSetMAC_LEAVE_L0_INFO_dp_redp_eq_enter_rcv(unsigned int udp_redp_eq_enter_rcv);
int iSetMAC_LEAVE_L0_INFO_up_retrain_redo_req(unsigned int uup_retrain_redo_req);
int iSetMAC_GEN4_LOW_SKP_CFG_resver(unsigned int uresver);
int iSetMAC_GEN4_LOW_SKP_CFG_reg_skp_intvl_srns_gen4(unsigned int ureg_skp_intvl_srns_gen4);
int iSetMAC_GEN4_LOW_SKP_CFG_resvered(unsigned int uresvered);
int iSetMAC_GEN4_LOW_SKP_CFG_reg_skp_intvl_sris_gen4(unsigned int ureg_skp_intvl_sris_gen4);
int iSetDFX_APB_LANE_ERROR_STATUS_0_pcs_rcv_err_status(unsigned int upcs_rcv_err_status);
int iSetDFX_APB_LANE_ERROR_STATUS_0_symbol_unlock_err_status(unsigned int usymbol_unlock_err_status);
int iSetDFX_APB_LANE_ERROR_STATUS_1_loopback_link_data_err_status(unsigned int uloopback_link_data_err_status);
int iSetDFX_APB_LANE_ERROR_STATUS_1_phy_lane_err_status(unsigned int uphy_lane_err_status);
int iSetREG_FIX_LP_8G_TX_COEFF_reg_8g_eq_fix_lp_tx_use_preset(unsigned int ureg_8g_eq_fix_lp_tx_use_preset);
int iSetREG_FIX_LP_8G_TX_COEFF_resvered(unsigned int uresvered);
int iSetREG_FIX_LP_8G_TX_COEFF_reg_8g_eq_fix_lp_tx_coeff(unsigned int ureg_8g_eq_fix_lp_tx_coeff);
int iSetREG_FIX_LP_16G_TX_COEFF_reg_16g_eq_fix_lp_tx_use_preset(unsigned int ureg_16g_eq_fix_lp_tx_use_preset);
int iSetREG_FIX_LP_16G_TX_COEFF_resvered(unsigned int uresvered);
int iSetREG_FIX_LP_16G_TX_COEFF_reg_16g_eq_fix_lp_tx_coeff(unsigned int ureg_16g_eq_fix_lp_tx_coeff);
int iSetREG_RXIDLE_DELAY_TIME_resvered(unsigned int uresvered);
int iSetREG_RXIDLE_DELAY_TIME_reg_rxeleidle_delay_time(unsigned int ureg_rxeleidle_delay_time);
int iSetMAC_REG_16G_PHY_EQ_FB_SEL_reg_up_8g_eqts2_sent_en(unsigned int ureg_up_8g_eqts2_sent_en);
int iSetMAC_REG_16G_PHY_EQ_FB_SEL_cfg_16g_reset_eieos(unsigned int ucfg_16g_reset_eieos);
int iSetMAC_REG_16G_PHY_EQ_FB_SEL_cfg_16g_merit_step(unsigned int ucfg_16g_merit_step);
int iSetMAC_REG_16G_PHY_EQ_FB_SEL_reg_16g_coeff_search_len(unsigned int ureg_16g_coeff_search_len);
int iSetMAC_REG_16G_PHY_EQ_FB_SEL_reg_16g_phy_eq_fb_sel(unsigned int ureg_16g_phy_eq_fb_sel);
int iSetMAC_REG_TX_MARGIN_CTRL_reg_tx_margin_mask(unsigned int ureg_tx_margin_mask);
int iSetMAC_REG_TX_MARGIN_CTRL_reg_tx_margin_mask_value(unsigned int ureg_tx_margin_mask_value);
int iSetMAC_REG_UP_8GT_EQTS2_PRESET_0_reg_up_8gt_eqts2_preset_0(unsigned int ureg_up_8gt_eqts2_preset_0);
int iSetMAC_REG_UP_8GT_EQTS2_PRESET_1_reg_up_8gt_eqts2_preset_1(unsigned int ureg_up_8gt_eqts2_preset_1);
int iSetREG_RXVALID_DELAY_TIME_resvered(unsigned int uresvered);
int iSetREG_RXVALID_DELAY_TIME_reg_rxvalid_delay_time(unsigned int ureg_rxvalid_delay_time);

#endif // __HIPCIEC_MAC_REG_1_C_UNION_DEFINE_H__
